Studies have shown that monolithic 3D ( M3D ) ICs outperform the existing through-silicon-via ( TSV ) -based 3D ICs in terms of power, performance, and area ( PPA ) metrics, primarily due to the orders of magnitude denser vertical interconnections offered by the nano-scale monolithic inter-tier vias. In order to facilitate faster industry adoption of the M3D technologies, physical design tools and methodologies are essential. Recent academic efforts in developing an EDA algorithm for 3D ICs, mainly targeting placement using TSVs, are inadequate to provide commercial-quality GDS layouts. Lately, pseudo-3D approaches have been devised, which utilize commercial 2D IC EDA engines with tricks that help them operate as an efficient 3D IC CAD tool. In this article, we provide thorough discussions and fair comparisons (both qualitative and quantitative) of the state-of-the-art pseudo-3D design flows, with analysis of limitations in each design flow and solutions to improve their PPA metrics. Moreover, we suggest a hybrid pseudo-3D design flow that achieves both benefits. Our enhancements and the inter-mixed design flow, provide up to an additional 26% wirelength, 10% power consumption, and 23% of power-delay-product improvements.

中文翻译：

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单片 3D IC 的伪 3D 物理设计流程：比较和增强

研究表明，单片 3D(M3D) IC 的表现优于现有的硅通孔(硅通孔) 基于 3D IC 的功率、性能和面积(购电协议) 指标，主要是由于纳米级单片层间通孔提供的数量级更密集的垂直互连。为了促进行业更快地采用 M3D 技术，物理设计工具和方法是必不可少的。最近在开发 3D IC 的 EDA 算法（主要针对使用 TSV 的布局）方面的学术努力不足以提供商业质量的 GDS 布局。最近，伪3D已经设计了一些方法，这些方法利用商业 2D IC EDA 引擎和技巧，帮助它们作为高效的 3D IC CAD 工具运行。在本文中，我们对最先进的伪 3D 设计流程进行了彻底的讨论和公平的比较（定性和定量），并分析了每个设计流程中的限制以及改进其 PPA 指标的解决方案。此外，我们建议实现这两个好处的混合伪 3D 设计流程。我们的增强功能和相互混合的设计流程提供了高达 26% 的额外线长、10% 的功耗和 23% 的功率延迟产品改进。