The quasi-cyclic (QC) low-density parity-check (LDPC) code is a key error correction code for the fifth generation (5G) of cellular network technology. Designed to support several frame sizes and code rates, the 5G LDPC code structure allows high parallelism to deliver the high demanding data rate of 10 Gb/s. This impressive performance introduces challenging constraints on the hardware design. Particularly, allowing such high flexibility can introduce processing rate penalties on some configurations. In this context, a novel highly parallel and flexible hardware architecture for the 5G LDPC decoder is proposed, targeting field-programmable gate array (FPGA) devices. The architecture supports frame parallelism to maximize the utilization of the processing units, significantly improving the processing rate. The controller unit was carefully designed to support all 5G configurations and to avoid update conflicts. Furthermore, an efficient data scheduling is proposed to increase the processing rate. Compared to the recent related state of the art, the proposed FPGA prototype achieves a higher processing rate per hardware resource for most configurations.

中文翻译：

---

面向 FPGA 的并行且灵活的 5G LDPC 解码器架构

准循环 (QC) 低密度奇偶校验 (LDPC) 码是第五代 (5G) 蜂窝网络技术的关键纠错码。5G LDPC 代码结构旨在支持多种帧大小和码率，可实现高并行度，以提供 10 Gb/s 的高要求数据速率。这种令人印象深刻的性能给硬件设计带来了挑战性的限制。特别是，允许​​如此高的灵活性会在某些配置上引入处理速率损失。在此背景下，针对现场可编程门阵列 (FPGA) 设备，提出了一种用于 5G LDPC 解码器的新型高度并行且灵活的硬件架构。该架构支持帧并行，最大限度地提高处理单元的利用率，显着提高处理速率。控制器单元经过精心设计，可支持所有 5G 配置并避免更新冲突。此外，提出了有效的数据调度以提高处理速率。与最近相关的现有技术相比，对于大多数配置，所提出的 FPGA 原型实现了每个硬件资源的更高处理速率。