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Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization Using SMT
IEEE Transactions on Very Large Scale Integration (VLSI) Systems ( IF 2.8 ) Pub Date : 2021-03-30 , DOI: 10.1109/tvlsi.2021.3065639
Chung-Kuan Cheng , Chia-Tung Ho , Daeyeal Lee , Bill Lin , Dongwon Park

With the relentless scaling of technology nodes, design technology co-optimization (DTCO) for the conventional (Conv.) cell structure is starting to reach its limitations due to limited routing resources, lateral p-n separations, and performance requirements. As a result, system technology co-optimization (STCO) has been proposed to exploit the benefits of 3-D architectures. Complementary-FET (CFET) technology, which stacks p-FET on n-FET or vice versa, can release the restriction of p-n separation and reduce in-cell routing congestion by enabling p-n direct connections. However, CFET standard cell (SDC) synthesis demands holistic considerations to maximize the area benefit of scaling at the block level due to the extremely limited routability that comes from the stacked structure and reduced cell height. In this article, we propose a satisfiability modulo theory (SMT)-based CFET SDC synthesis framework that simultaneously solves place-and-route to generate optimized layouts. We first demonstrate that the CFET structure achieves 10.94% and 21.27% reduction on average cell area and metal length, respectively, and 15.10% smaller block-level area compared to Conv. structure as scaling down to 3.5T architecture. For routability, the proposed constraint-based minimum pin length/minimum pin opening and objective-based edge-based pin-separation/M2 track use reduce up to 48% #DRVs at the block level compared to the previous work. Then, through extensive DTCO explorations on ground design rules and #BEOLs, 3.5T CFET SDCs achieve up to 6.50% smaller block-level areas than 4.5T CFET SDCs. Finally, with the assistance of STCO and DTCO, 3.5T CFET SDCs achieve 21.0% on average reduced block-level areas compared to 4.5T Conv. SDCs.

中文翻译:

使用 SMT 进行设计和系统技术协同优化的互补 FET (CFET) 标准单元合成框架

随着技术节点的不断扩展,传统 (Conv.) 单元结构的设计技术协同优化 (DTCO) 由于有限的布线资源、横向 pn 分离和性能要求而开始达到其局限性。因此,已提出系统技术协同优化 (STCO) 以利用 3-D 架构的优势。互补 FET (CFET) 技术将 p-FET 堆叠在 n-FET 上,反之亦然,它可以通过启用 pn 直接连接来解除 pn 分离的限制并减少单元内布线拥塞。然而,CFET 标准单元 (SDC) 综合需要全面考虑,以最大限度地提高块级缩放的面积优势,因为堆叠结构和降低的单元高度导致的可布线性极其有限。在本文中,我们提出了一种基于可满足性模理论 (SMT) 的 CFET SDC 综合框架,该框架同时解决布局布线以生成优化布局。我们首先证明,与 Conv 相比,CFET 结构的平均单元面积和金属长度分别减少了 10.94% 和 21.27%,并且块级面积减少了 15.10%。结构缩小到 3.5T 架构。对于可布线性,与之前的工作相比,所提出的基于约束的最小引脚长度/最小引脚开口和基于目标的基于边缘的引脚分离/M2 轨道使用在块级别减少了多达 48% 的#DRV。然后,通过对接地设计规则和#BEOL 的广泛 DTCO 探索,3.5T CFET SDC 实现的块级面积比 4.5T CFET SDC 小 6.50%。最后,在STCO和DTCO的帮助下,3.5T CFET SDC达到了21。与 4.5T Conv. 相比,平均减少了 0% 的块级区域。SDC。
更新日期:2021-06-04
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