In this article, a nonlinear capacitance model for a large-signal compact model of partially depleted (PD) silicon-on-insulator (SOI) transistors is proposed. When the transistors are operated in the saturation and triode region, the gate–source capacitance ( $C_{\mathrm {gs}}$ ) and the gate–drain capacitance ( $C_{\mathrm {gd}}$ ) change with the gate–source voltage ( $V_{\mathrm {GS}}$ ) nonlinearly. $C_{\mathrm {gs}}$ will emerge a significant compression phenomenon in the triode region. This capacitance model adds a hyperbolic tangent function to the conventional model’s function to characterize this phenomenon. Besides, the nonlinear drain current model is obtained on the basis of a unified empirical model. To validate this improved large-signal equivalent circuit model, two different transistors are manufactured in a commercial 180-nm body-contact (BC) PD-SOI process. On-wafer measurement is implemented to obtain the experimental data. Then the calculated results of the model are compared with the measurement data. The relative root-mean-square-error (RRMSE) is less than 6.59% for output power, 9.03% for power-added efficiency (PAE), and 2.72% for the gain respectively.

中文翻译：

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部分耗尽型绝缘体上硅 MOSFET 的改进大信号等效电路模型

在本文中，提出了一种用于部分耗尽型 (PD) 绝缘体上硅 (SOI) 晶体管的大信号紧凑模型的非线性电容模型。当晶体管工作在饱和区和三极管区时，栅源电容（ $C_{\mathrm {gs}}$ ) 和栅漏电容 ( $C_{\mathrm {gd}}$ ) 随栅源电压 ( $V_{\mathrm {GS}}$ ) 非线性。 $C_{\mathrm {gs}}$ 三极管区域会出现明显的压缩现象。该电容模型在传统模型的函数中添加了双曲正切函数来表征这种现象。此外，非线性漏电流模型是在统一经验模型的基础上获得的。为了验证这种改进的大信号等效电路模型，采用商用 180 纳米体接触 (BC) PD-SOI 工艺制造了两种不同的晶体管。实施晶圆上测量以获得实验数据。然后将模型的计算结果与测量数据进行比较。输出功率的相对均方根误差 (RRMSE) 分别小于 6.59%、功率附加效率 (PAE) 的 9.03% 和增益的 2.72%。