This paper presents an electrical characterization and a compact modeling of FD-SOI four-gate qubit MOS devices, carried out at room temperature and in linear regime. The main figures of merit are extracted from average drain current curves using Y – function method. Poisson solver-based simulations are performed to interpret the experimental data, in particular the influence among gates and the effective channel length modulation. Furthermore, a drain current matching analysis between gates is conducted, and the main variability parameters are extracted. Our results, despite the unconventional device engineering, show a variability performance comparable to the state-of-the-art 28nm FD-SOI technology. Finally, a Lambert function based model is developed to validate both the electrical and statistical characterization. It is assumed, according to the experimental data, that the four gate device can be modeled as the series of four identical and independent transistors. Including the contribution of source and drain access resistance it has been possible to reproduce the device behavior at high external gates voltages.

中文翻译：

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室温下 FDSOI 四栅极量子位 MOS 器件的统计和电气建模

本文介绍了在室温和线性状态下进行的 FD-SOI 四栅极量子位 MOS 器件的电气特性和紧凑建模。主要的品质因数是使用 Y 函数方法从平均漏极电流曲线中提取的。执行基于泊松求解器的模拟来解释实验数据，特别是门和有效通道长度调制之间的影响。此外，还进行了栅极之间的漏极电流匹配分析，并提取了主要的可变性参数。尽管采用了非常规的器件工程，但我们的结果显示出与最先进的 28nm FD-SOI 技术相当的可变性能。最后，开发了一个基于朗伯函数的模型来验证电气和统计特性。据推测，根据实验数据，可以将四门器件建模为四个相同且独立的晶体管的串联。包括源极和漏极访问电阻的贡献，可以在高外栅极电压下重现器件行为。