This paper presents an improved 8 × 8-bit Booth multiplier with reduced power, delay and area. The major operations that consume power and are responsible for larger critical path delays in Booth multiplication are partial product array generation (PPAG), partial product array compression (PPAC) and partial product array addition (PPAA), for the generation of the final product. So, in our proposed multiplication framework, the design improvements are focused on B-to-C, PPAG, PPAC and PPAA. For speed-power improvement in PPAG operations, an improved circuit for binary-to-two’s complement converter has been proposed to provide a lower critical path delay. Secondly, for power-area improvement, we have proposed a new scheme to generate the first term for all PPAs, the encoder for the generation of the first partial product array (PPA) and modified encoders for third PPA. This results in reduced multiplexer sizes, leading to lower power consumption and lower delays during PPAG. For speed-power improvement in the partial product array addition (PPAA), the carry save addition scheme without carry propagation has been proposed for the reduction of partial product arrays that speeds up the PPAC operation. For the final addition of the last two operands, i.e. PPAA, an n-bit adder segment is designed for our proposed 13-bit modified carry select adder (MCSA) that provides a major contribution in the speed-power and area efficiency of the proposed Booth multiplier architecture. The proposed architecture along with some recently reported state-of-the-art architectures is implemented in 1P-9 M Low K 90-nm CMOS technology, and simulations are carried out using Cadence Virtuoso using 500 MHz clock pulse frequency at a temperature of 27 °C using supply voltage of 1.25 V, for comparison purposes. The proposed multiplier provides an improvement of 26.12% in delay, 32.9% improvement in power-delay product and 32.36% improvement in area-delay product, as compared to the recent designs.

本文介绍了一种改进的 8 × 8 位 Booth 乘法器，其功耗、延迟和面积均有所降低。消耗功率并导致布斯乘法中较大关键路径延迟的主要操作是部分乘积阵列生成 (PPAG)、部分乘积阵列压缩 (PPAC) 和部分乘积阵列加法 (PPAA)，用于生成最终乘积。因此，在我们提出的乘法框架中，设计改进主要集中在 B-to-C、PPAG、PPAC 和 PPAA。为了提高 PPAG 操作中的速度-功率，已经提出了一种用于二进制到二进制补码转换器的改进电路，以提供较低的关键路径延迟。其次，为了改善功率面积，我们提出了一个新方案来为所有 PPA 生成第一项，用于生成第一个部分乘积数组 (PPA) 的编码器和用于第三个 PPA 的修改后的编码器。这导致多路复用器尺寸减小，从而降低 PPAG 期间的功耗和延迟。为了提高部分乘积阵列加法 (PPAA) 的速度-功率，提出了没有进位传播的进位保存加法方案，以减少部分乘积阵列，从而加快 PPAC 操作。对于最后两个操作数的最后加法，即 PPAA，为我们提出的 13 位修改进位选择加法器 (MCSA) 设计了一个 n 位加法器段，它对所提出的速度-功率和面积效率做出了重大贡献。展位乘法器架构。提议的架构以及最近报道的一些最先进的架构是在 1P-9 M Low K 90-nm CMOS 技术中实现的，并且使用 Cadence Virtuoso 进行了模拟，使用 500 MHz 时钟脉冲频率，温度为 27 °C 使用 1.25 V 电源电压，用于比较。与最近的设计相比，所提议的乘法器提供了 26.12% 的延迟改进、32.9% 的功率延迟乘积改进和 32.36% 的面积延迟乘积改进。