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A novel deep gate power MOSFET in partial SOI technology for achieving high breakdown voltage and low lattice temperature
Journal of Computational Electronics ( IF 2.1 ) Pub Date : 2021-05-31 , DOI: 10.1007/s10825-021-01724-5
Amir Gavoshani , Ali A. Orouji

We propose a novel deep gate lateral double diffused metal-oxide-semiconductor (LDMOS) field-effect transistor in partial silicon-on-insulator (PSOI) technology for achieving high breakdown voltage and reduced power dissipation. In the proposed device, an N+ well is inserted in the buried oxide under the drain region. By optimizing the N+ well and the lateral distance between the buried oxide and the left side of the device, the electric field is modified. Therefore, the breakdown voltage improves. Also, the PSOI technology used in the proposed structure has a significant effect on reducing the lattice temperature. Our simulation results show that the proposed structure improves the breakdown voltage by about 67.5% and reduces the specific on-resistance by about 20% in comparison with a conventional LDMOS.



中文翻译:

采用部分 SOI 技术的新型深栅功率 MOSFET 可实现高击穿电压和低晶格温度

我们提出了一种采用部分绝缘体上硅 (PSOI) 技术的新型深栅横向双扩散金属氧化物半导体 (LDMOS) 场效应晶体管,以实现高击穿电压和降低功耗。在所提出的器件中,N +阱被插入到漏区下方的掩埋氧化物中。通过优化 N +以及掩埋氧化物与器件左侧之间的横向距离,电场被修改。因此,击穿电压提高。此外,所提出结构中使用的 PSOI 技术对降低晶格温度具有显着影响。我们的仿真结果表明,与传统的 LDMOS 相比,所提出的结构将击穿电压提高了约 67.5%,并将比导通电阻降低了约 20%。

更新日期:2021-06-01
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