Cryogenic computing can achieve high performance and power efficiency by dramatically reducing the device’s leakage power and wire resistance at low temperatures. Recent advances in cryogenic computing focus on developing cryogenic-optimal cache and memory devices to overcome memory capacity, latency, and power walls. However, little research has been conducted to develop a cryogenic-optimal core architecture even with its high potentials in performance, power, and area efficiency. In this article, we first develop CryoCore-Model, a cryogenic processor modeling framework that can accurately estimate the maximum clock frequency of processor models running at 77 K. Next, driven by the modeling tool, we design CryoCore, a 77 K-optimal core microarchitecture to maximize the core’s performance and area efficiency while minimizing the cooling cost. The proposed cryogenic processor architecture, in this article, achieves the large performance improvement and power reduction and, thus, contributes to the future of high-performance and power-efficient computer systems.

中文翻译：

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下一代低温处理器架构

低温计算可以通过在低温下显着降低设备的泄漏功率和线电阻来实现高性能和电源效率。低温计算的最新进展侧重于开发低温优化缓存和内存设备，以克服内存容量、延迟和电源墙。然而，即使在性能、功率和面积效率方面具有很高的潜力，也很少有人研究开发低温优化的核心架构。在本文中，我们首先开发了 CryoCore-Model，一个低温处理器建模框架，可以准确估计运行在 77 K 的处理器模型的最大时钟频率。 接下来，在建模工具的驱动下，我们设计了 CryoCore，一个 77 K 最优内核微架构，最大限度地提高核心的性能和面积效率，同时最大限度地降低冷却成本。