In this paper, we explore the use of a 180 nm CMOS single-poly technology platform for realizing analog Deep Neural Network integrated circuits. The analysis focuses on analog vector–matrix multiplier architectures, one of the main building blocks of a neural network, implementing in-memory computation using Floating-Gate multi-level non-volatile memories. We present two memory options, suited either for current-mode or for time-domain vector–matrix multiplier implementations, with low–voltage charge-injection program and erase operations. The effects of a limited accuracy are also investigated through system-level simulations, by accounting for the temperature dependence of the stored weights and the corresponding impact on the network error rate.

在本文中，我们探索了使用 180 nm CMOS 单晶硅技术平台来实现模拟深度神经网络集成电路。分析侧重于模拟向量矩阵乘法器架构，它是神经网络的主要构建块之一，使用浮栅多级非易失性存储器实现内存计算。我们提出了两种存储器选项，适用于电流模式或时域矢量矩阵乘法器实现，具有低电压电荷注入程序和擦除操作。通过考虑存储权重的温度依赖性和对网络错误率的相应影响，还通过系统级模拟研究了有限精度的影响。