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The design, analysis, and cost estimation of a generic adder and subtractor using the layered T (LT) logic reduction methodology with a quantum-dot cellular-automata-based approach
Journal of Computational Electronics ( IF 2.1 ) Pub Date : 2021-05-27 , DOI: 10.1007/s10825-021-01712-9
Chiradeep Mukherjee , Saradindu Panda , Asish Kumar Mukhopadhyay , Bansibadan Maji

The quantum-dot cellular automata (QCA) is considered to be one of the ground-breaking nanotechnologies developed over the last two decades. A layered T (LT) logic cell library is constructed herein, and the methodology is extended to generic adder and subtractor module designs. The two proposed algorithms lead to more efficient QCA layout designs for an n-bit ripple carry adder (RCA) and subtractor based on an effective clock zone assignment approach. The suggested one-, four-, and eight-bit RCAs and subtractors surpass most of their existing counterparts by offering lower effective area and cell complexity. A comparative analysis is presented regarding the complexity, irreversible power dissipation, and Costα of the proposed n-bit layouts from a cost estimation purview.



中文翻译:

使用分层 T (LT) 逻辑归约方法和基于量子点元胞自动机的方法设计、分析和成本估算通用加法器和减法器

量子点元胞自动机(QCA)被认为是过去二十年发展起来的突破性纳米技术之一。这里构建了一个分层的 T (LT) 逻辑单元库,并将该方法扩展到通用加法器和减法器模块设计。两种提出的算法基于有效的时钟区域分配方法,为n位波纹进位加法器(RCA)和减法器带来了更有效的QCA布局设计。建议的 1 位、4 位和 8 位 RCA 和减法器通过提供较低的有效面积和单元复杂度超越了大多数现有的对应物。提出了关于拟议n的复杂度,不可逆功耗和成本α的比较分析。成本估算范围的位布局。

更新日期:2021-05-28
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