Cell-aware test (CAT) explicitly targets faults caused by defects inside library cells to improve test quality, compared with conventional automatic test pattern generation (ATPG) approaches, which target faults only at the boundaries of library cells. The CAT methodology consists of two stages. Stage 1, based on dedicated analog simulation, library characterization per cell identifies which cell-level test pattern detects which cell-internal defect; this detection information is encoded in a defect detection matrix (DDM). In Stage 2, with the DDMs as inputs, cell-aware ATPG generates chip-level test patterns per circuit design that is build up of interconnected instances of library cells. This paper focuses on Stage 1, library characterization, as both test quality and cost are determined by the set of cell-internal defects identified and simulated in the CAT tool flow. With the aim to achieve the best test quality, we first propose an approach to identify a comprehensive set, referred to as full set, of potential open- and short-defect locations based on cell layout. However, the full set of defects can be large even for a single cell, making the time cost of the defect simulation in Stage 1 unaffordable. Subsequently, to reduce the simulation time, we collapse the full set to a compact set of defects which serves as input of the defect simulation. The full set is stored for the diagnosis and failure analysis. With inspecting the simulation results, we propose a method to verify the test quality based on the compact set of defects and, if necessary, to compensate the test quality to the same level as that based on the full set of defects. For 351 combinational library cells in Cadence’s GPDK045 45nm library, we simulate only 5.4% defects from the full set to achieve the same test quality based on the full set of defects. In total, the simulation time, via linear extrapolation per cell, would be reduced by 96.4% compared with the time based on the full set of defects.

与传统的自动测试模式生成（ATPG）方法相比，单元感知测试（CAT）明确地针对库单元内部缺陷引起的故障，以提高测试质量，后者仅将故障定位在库单元的边界。CAT方法包括两个阶段。第1阶段，基于专用的模拟仿真，每个单元的库特征确定了哪个单元级测试模式检测到了哪个单元内部缺陷；该检测信息被编码在缺陷检测矩阵中（DDM）。在阶段2中，以DDM为输入，单元感知型ATPG在电路设计的基础上生成芯片级测试模式，该电路设计是由库单元的互连实例构成的。本文着重于第1阶段，库表征，因为测试质量和成本均由在CAT工具流程中识别和模拟的一组单元内部缺陷确定。为了获得最佳的测试质量，我们首先提出一种方法来识别一个完整的集合，称为完整集合，基于单元格布局的潜在的开放和短缺陷位置。但是，即使对于单个单元，全套缺陷也可能很大，这使得阶段1中进行缺陷仿真的时间成本难以承受。随后，为了减少仿真时间，我们将全套压缩为一组紧凑的缺陷，以作为缺陷仿真的输入。完整的存储信息将用于诊断和故障分析。通过检查仿真结果，我们提出了一种基于紧凑缺陷集来验证测试质量的方法，并在必要时将测试质量补偿到与基于完整缺陷集相同的水平。对于Cadence的GPDK045 45nm库中的351个组合库单元，我们仅模拟全套中的5.4％缺陷，以基于全部缺陷实现相同的测试质量。总共，