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Impact of Thermal Effects on the Performance of the Power Gating Circuits Using NEMS, FinFETs, and NWFETs
IEEE Transactions on Electron Devices ( IF 3.1 ) Pub Date : 2021-05-03 , DOI: 10.1109/ted.2021.3074349
Sumit Saha , U. Sajesh Kumar , Maryam Shojaei Baghini , Mayank Goel , V. Ramgopal Rao

In this article, the power gating (PG) technique is analyzed using nano-electro-mechanical switches (NEMS), FinFETs, and nanowire field-effect transistors (NWFETs). We have used detailed circuit level simulations using well-calibrated models to obtain the conditions for net energy saving with thermal effects. We demonstrate that for a benchmark 17-stage buffer chain circuit, the NEMS PG will be superior to sub-10-nm FinFETs and NWFETs-based gating when the $ {T}_{ \text{on}}/ {T}_{ \text{off}}$ ratio is less than 0.1 at room temperature. The ratio increases as temperature increases. Circuit simulations show that the energy gain ( $ {T}_{\text {on}}/ {T}_{ \text{off}} = {10}^{-{4}}$ ) due to NEMS gating increases by 3.6 times with reference to NWFETs and 7.3 times as compared to FinFETs-based gating when the temperature increases from 30 °C to 80 °C. NWFETs require a longer breakeven cycle for PG to become more energy-efficient than FinFETs due to its better gate control over the channel.

中文翻译:

使用NEMS,FinFET和NWFET的热效应对功率门控电路性能的影响

在本文中,使用纳米机电开关(NEMS),FinFET和纳米线场效应晶体管(NWFET)分析了功率门控(PG)技术。我们已经使用经过良好校准的模型进行了详细的电路级仿真,以获得通过热效应实现净节能的条件。我们证明,对于基准的17级缓冲链电路,NEMS PG将在低于10nm的FinFET和基于NWFET的门控条件下胜出。 $ {T} _ {\ text {on}} / {T} _ {\ text {off}} $ 室温下该比率小于0.1。该比率随着温度的升高而增加。电路仿真表明,能量增益( $ {T} _ {\ text {on}} / {T} _ {\ text {off}} = {10} ^ {-{4}} $ )是由于温度从30°C升至80°C时,基于NEMS的门控相对于基于FinFET的门控增加了3.6倍,而与基于FinFET的门控相比增加了7.3倍。NWFET由于需要更好的通道栅极控制,因此与FinFET相比,PG需要更长的盈亏平衡周期才能变得更加节能。
更新日期:2021-05-25
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