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Structural and Electrical Characteristics of ALD-TiO2/SiON/n-Si Gate-Stack for Advanced CMOS Device Applications
IEEE Transactions on Electron Devices ( IF 3.1 ) Pub Date : 2021-05-06 , DOI: 10.1109/ted.2021.3075394
Richa Gupta , Rakesh Vaid

We report the fabrication and characterization of atomic layer deposition (ALD)-titanium oxide (TiO 2 )/ silicon oxynitride (SiON)/n-Si gate-stack with ultrathin SiON (~4.46 nm) as an interfacial layer (IL) grown prior on the Si substrate followed by postdeposition annealing (PDA) of ALD-TiO 2 in O 2 ambient and N 2 ambient. The structural characterization comprises the atomic force microscopy (AFM), the Fourier transform infrared spectroscopy (FTIR), the field emission scanning electron microscopy (FESEM), and the energy-dispersive X-ray spectroscopy (EDAX), whereas the electrical characterization includes capacitance–voltage ( ${C}$ ${V}$ ), conductance–voltage ( ${G}$ ,– ${V}$ ), and current–voltage ( ${I}$ ${V}$ ) measurements for the extraction of dielectric constant ( ${k}$ ), interface trap density ( ${D}_{it}$ ), effective oxide thickness (EOT), series resistance ( ${R}_{s}$ ), leakage current density (J), effective oxide charge ( ${Q}_{eff}$ ), barrier height ( $\Phi _{bo}$ ), ideality factor ( $\eta $ ), and breakdown voltage ( ${V}_{br}$ ). The determined values of ${k}$ , ${D}_{it}$ , EOT, ${R} _{s}$ , ${J}$ , ${Q}_{eff}, \Phi _{bo}$ , $\eta $ , and ${V}_{br}$ are 44, $6.3\times 10^{12}$ eV −1 cm −2 , 1.4 nm, 0.0623 $\text{K}\Omega $ , $2.5\times 10^{-10}$ A/cm 2 , $0.76\times 10 ^{15}$ cm −2 , 0.423, 1.6, and −0.34, respectively. The pregrowth of SiON IL prior to TiO 2 deposition has passivated the traps at the interface of SiON/TiO 2 , and the annealing of TiO 2 film in N 2 ambient has further worked over the existing challenges associated with scalability and gate leakage current.

中文翻译:

先进CMOS器件应用的ALD-TiO 2 / SiON / n-Si栅堆叠的结构和电气特性

我们报告了原子层沉积(ALD)-氧化钛(TiO 2 )/氮氧化硅(SiON)/ n-Si栅叠层的制造和表征,该层 具有先前生长的超薄SiON(〜4.46 nm)作为界面层(IL)在Si衬底上进行沉积,然后在O 2环境和N 2环境中对ALD-TiO 2进行 后沉积退火(PDA) 。结构表征包括原子力显微镜(AFM),傅立叶变换红外光谱(FTIR),场发射扫描电子显微镜(FESEM)和能量色散X射线光谱(EDAX),而电学特征包括电容-电压 ( $ {C} $ $ {V} $ ),电导-电压( $ {G} $ ,– $ {V} $ )和电流-电压( $ {I} $ $ {V} $ )测量介电常数( $ {k} $ ),界面陷阱密度( $ {D} _ {it} $ ),有效氧化物厚度(EOT),串联电阻( $ {R} _ {s} $ ),漏电流密度(J),有效氧化物电荷( $ {Q} _ {eff} $ ),障碍物高度( $ \ Phi _ {bo} $ ),理想因子( $ \ eta $ )和击穿电压( $ {V} _ {br} $ )。的确定值 $ {k} $ $ {D} _ {it} $ ,EOT, $ {R} _ {s} $ $ {J} $ $ {Q} _ {eff},\ Phi _ {bo} $ $ \ eta $ , 和 $ {V} _ {br} $ 是44 $ 6.3 \乘以10 ^ {12} $ 电子伏特 -1 厘米 -2 ,1.4纳米,0.0623 $ \ text {K} \ Omega $ $ 2.5 \乘以10 ^ {-10} $ A / cm 2 $ 0.76 \乘以10 ^ {15} $ 厘米 -2 ,0.423,1.6,和-0.34,分别。在TiO 2沉积之前,SiON IL的预生长 已经钝化了SiON / TiO 2界面处的陷阱 ,并且在N 2环境中TiO 2膜 的退火 进一步解决了与可扩展性和栅极泄漏电流相关的现有挑战。
更新日期:2021-05-25
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