In this study, p-type Pi-gate (PG) poly-Si nanowire channel junctionless accumulation-mode (JAM) field-effect transistors (FETs) were successfully fabricated and their reliability was investigated. The reliability of these PG JAM FETs was found to be dependent on the effective channel doping concentration ( ${N}_{\text {ch,eff}}$ ). Through a negative gate bias stress (NGBS) test, we found that degradation in the average subthreshold swing (A.S.S.) and shift in the threshold voltage ( ${V}_{\text {TH}}$ ) increases as the ${N}_{\text {ch,eff}}$ of the PG JAM FETs decreases. Furthermore, the PG JAM FETs with a lower ${N}_{\text {ch,eff}}$ show the more severe rate of deterioration in the transconductance ( ${G}_{\text {m}}$ ) and ON current ( ${I}_{\text {ON}}$ ). By increasing ${N}_{\text {ch,eff}}$ to reduce the electric field ( ${E}$ -field) on the gate oxide and tune the carrier transport mechanism in the poly-Si nanowire channel, a better immunity against the NGBS test in the p-type PG JAM FETs can be achieved under a gate overdrive voltage ( ${V}_{\text {GOD}} = {V}_{G}$ – ${V}_{\text {TH},\text {initial}} = -{3.5}$ V) to perform the NGBS test.

中文翻译：

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p型Pi-Gate多晶硅纳米线沟道无结累积模式FET的可靠性

在这项研究中，成功​​地制造了p型Pi栅极（PG）多晶硅纳米线沟道无结累积模式（JAM）场效应晶体管（FET）并对其可靠性进行了研究。发现这些PG JAM FET的可靠性取决于有效的沟道掺杂浓度（ $ {N} _ {\ text {ch，eff}} $ ）。通过负栅极偏置应力（NGBS）测试，我们发现平均亚阈值摆幅（ASS）下降并且阈值电压（ $ {V} _ {\ text {TH}} $ ）随着 $ {N} _ {\ text {ch，eff}} $ PG JAM FET的数量减少。此外，PG JAM FET具有较低的 $ {N} _ {\ text {ch，eff}} $ 显示跨导的恶化速度更严重（ $ {G} _ {\ text {m}} $ ）和ON电流（ $ {I} _ {\ text {ON}} $ ）。通过增加 $ {N} _ {\ text {ch，eff}} $ 减少电场（ $ {E} $ 场）并调整多晶硅纳米线通道中的载流子传输机制，可以在栅极过驱动电压（p型PG JAM FET）下获得更好的NGBS测试抗扰性 $ {V} _ {\ text {GOD}} = {V} _ {G} $ – $ {V} _ {\ text {TH}，\ text {initial}} =-{3.5} $ V）执行NGBS测试。