Knowing exactly potentials’ distribution in pixels is a key to ensure that electronretention and transport enable a good pixel operation. Moreover, it is also a key parameter for controlof charge storage capabilityor fullwell capacity, strongly driven by potential barriers. In this article, a new method is presented to characterize potentialswithin pixels from test structure measurements. The proposed method enables to extract potential under a gate, pinning potential of photodiodes or memories, and any potential along the charge path. It is based on the use of the Enz–Krummenacher–Vittoz (EKV) model together with measurements on adequate test structures. Thanks to the so-called “ ${Y}$ function series resistance correction,” the method can even be applied to test structuresincludingdevices in series as in real pixel. The method proposed here is assessed using Sentaurus technologycomputer-aided design (TCAD) simulation results. Such potentials extracted on the test structure can be used for process and pixel developments, devicemonitoring, reliability studies, and TCAD calibration.

中文翻译：

---

基于EKV模型的测试结构CMOS像素电势提取方法

准确了解像素中的电势分布是确保电子保留和传输能够实现良好像素操作的关键。而且，它也是控制电荷存储能力或全阱能力的关键参数，这受到潜在势垒的强烈驱动。在本文中，提出了一种通过测试结构测量来表征像素内电势的新方法。所提出的方法使得能够提取栅极下的电势，光电二极管或存储器的钉扎电势以及沿着电荷路径的任何电势。它基于Enz-Krummenacher-Vittoz（EKV）模型的使用以及对适当测试结构的测量。多亏了所谓的“ $ {Y} $ 功能串联电阻校正”，该方法甚至可以应用于测试结构，包括与真实像素一样的串联器件。本文提出的方法是使用Sentaurus技术的计算机辅助设计（TCAD）仿真结果进行评估的。在测试结构上提取的此类电势可用于过程和像素开发，设备监控，可靠性研究和TCAD校准。