Many-core processors demand scalable, efficient and low latency NoCs. Bypass routers are an affordable solution to attain low latency in relatively simple topologies like the mesh. SMART improves on traditional bypass routers implementing multi-hop bypass which reduces the importance of the distance between pairs of nodes. Nevertheless, the conservative buffer reallocation policy of SMART requires a large number of Virtual Channels (VCs) to offer high performance, penalizing its implementation cost. Besides, SMART zero-load latency values highly depend on $HPC_{Max}$ , the maximum number of hops that can be jumped per cycle. In this article, we present Speculative-SMART++ (S-SMART++), with two mechanisms that significantly improve multi-hop bypass. First, zero-load latency is reduced by speculatively setting consecutive multi-hops. Second, the inefficient buffer reallocation policy of SMART is reduced by combining multi-packet buffers, Non-Empty Buffer Bypass and per-packet allocation. These proposals are evaluated using functional simulation, with synthetic and real loads, and synthesis tools. S-SMART++ does not need VCs to obtain the performance of SMART with 8 VCs, reducing notably logic resources and dynamic power. Additionally, S-SMART++ reduces the base-latency of SMART by at least 29.2 percent, even when using the biggest $HPC_{Max}$ possible.

中文翻译：

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S-SMART ++：利用推测性旁路请求的低延迟NoC

多核处理器需要可扩展，高效且低延迟的NoC。旁路路由器是一种经济实惠的解决方案，可在网状结构等相对简单的拓扑结构中获得低延迟。SMART在实现多跳旁路的传统旁路路由器上进行了改进，从而降低了节点对之间距离的重要性。但是，SMART的保守缓冲区重新分配策略需要大量的虚拟通道（VC）才能提供高性能，从而降低了其实现成本。此外，SMART零负载延迟值高度依赖于$ HPC_ {Max} $ ，每个周期可以跳的最大跳数。在本文中，我们介绍了Speculative-SMART ++（S-SMART ++），它具有两种可显着改善多跳旁路的机制。首先，通过推测性地设置连续的多跳来减少零负载等待时间。其次，通过组合多数据包缓冲区来减少SMART的无效缓冲区重新分配策略，非空缓冲区旁路和按数据包分配。这些建议是使用功能仿真，合成负载和实际负载以及合成工具进行评估的。S-SMART ++不需要VC即可获得具有8个VC的SMART的性能，从而显着减少了逻辑资源和动态功耗。此外，即使使用最大的S-SMART ++，SMART的基本延迟也会至少降低29.2％。$ HPC_ {Max} $ 可能的。