With the continued slowing of Moore?s law and Dennard scaling, it has become more imperative that hardware designers make the best use of domain-specific information to improve designs. Gone are the days when we could rely primarily on silicon process technology improvements to provide faster and more efficient computation. Instead, architectural improvements are necessary to provide improved performance, power reduction, and/or reduced cost. Nowhere is this more apparent than when looking at Deep Learning workloads. Cutting-edge techniques achieving state-of-the-art training accuracy demand ever-larger training data-sets and more-complex network topologies, which results in longer training times. At the same time, after training these networks, we expect them to be deployed widely. As a result, executing large networks efficiently becomes critical, whether that execution is done in a data center or in an embedded system. In this article, we look at trends in deep learning research that present new opportunities for domain-specific hardware architectures and explore how next-generation compilation tools might support them.

中文翻译：

---

深度学习领域特定计算的演变

随着摩尔定律和Dennard缩放比例的持续放慢，硬件设计人员必须充分利用特定于领域的信息来改进设计，这一点变得越来越重要。我们主要依靠硅工艺技术改进来提供更快，更高效的计算的日子已经一去不复返了。相反，必须进行体系结构改进以提供改进的性能，降低功耗和/或降低成本。在研究深度学习工作负载时，这没有什么比这更明显了。要实现最先进的培训准确性，最先进的技术需要越来越大的培训数据集和更复杂的网络拓扑，从而导致更长的培训时间。同时，在培训了这些网络之后，我们希望它们会得到广泛部署。因此，无论是在数据中心还是在嵌入式系统中执行，高效执行大型网络都变得至关重要。在本文中，我们将研究深度学习研究的趋势，这些趋势为特定领域的硬件体系结构提供了新的机会，并探讨了下一代编译工具如何支持它们。