In this work, the impact of interface trap charges (ITCs) on electrical characteristics of dielectric pocket SOI-TFET (DP SOI-TFET) proposed for the reduction of ambipolar conduction and improvement of high-frequency (HF) performances has been demonstrated in details. The reliability of DP SOI-TFET has been examined by analysing the impact of varying polarity and density of ITCs on dc and analog/HF performances of the proposed device. Through TCAD simulations, it has been shown that donor and acceptor ITCs existing at the interface between drain region and dielectric pocket (i.e. Si/DP) have significant impact on the parameters such as OFF-state current, ambipolar conduction, parasitic capacitances, output resistance, and cut-off frequency of DP SOI-TFET. Furthermore, a comparative analysis has been carried out between the conventional and DP SOI-TFET under influence of traps, and it has been found that performances of the proposed device are further improved by the existence of acceptor ITCs at higher negatively biased gate. Even though, the existence of donor ITCs at Si/DP interface has been found degrading the performances of the proposed DP SOI-TFET, simulation results suggest that dc and analog/HF figure of merits are still superior in the proposed device as compared to those in the conventional SOI-TFET.

在这项工作中，已详细证明了界面陷阱电荷（ITC）对介电袋SOI-TFET（DP SOI-TFET）的电学特性的影响，该介质旨在降低双极性传导并改善高频（HF）性能。 。DP SOI-TFET的可靠性已通过分析ITC的极性和密度变化对所提出器件的直流和模拟/ HF性能的影响进行了检验。通过TCAD仿真，已表明存在于漏极区和电介质腔（即Si / DP）之间的界面上的施主和受主ITC对诸如关态电流，双极性传导，寄生电容，输出电阻之类的参数具有重大影响。 ，以及DP SOI-TFET的截止频率。此外，在陷阱的影响下，对传统的SOI-TFET和DP SOI-TFET进行了比较分析，发现通过在更高的负偏置栅极处存在受体ITC，可以进一步改善所提出器件的性能。即使在Si / DP接口处存在施主ITC，也会降低所提议的DP SOI-TFET的性能，仿真结果表明，与拟议的器件相比，该器件的dc和模拟/ HF品质因数仍然更好在传统的SOI-TFET中。