Integration-technology feature shrink increases computing-system susceptibility to single-event effects (SEE). While modeling SEE faults will be critical, an integrated processor’s scope makes physically correct modeling computationally intractable. Without useful models, presilicon evaluation of fault-tolerance approaches becomes impossible. To incorporate accurate transistor-level effects at a system scope, we present a multiscale simulation framework. Charge collection at the 1) device level determines 2) circuit-level transient duration and state-upset likelihood. Circuit effects, in turn, impact 3) register-transfer-level architecture-state corruption visible at 4) the system level. Thus, the physically accurate effects of SEEs in large-scale systems, executed on a high-performance computing (HPC) simulator, could be used to drive cross-layer radiation hardening by design. We demonstrate the capabilities of this model with two case studies. First, we determine a D flip-flop’s sensitivity at the transistor level on 14-nm FinFet technology, validating the model against published cross sections. Second, we track and estimate faults in a microprocessor without interlocked pipelined stages (MIPS) processor for Adams 90% worst case environment in an isotropic space environment.

中文翻译：

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高级节点处理器中单事件引发的故障的多尺度系统建模

集成技术功能的缩减增加了计算系统对单事件效果（SEE）的敏感性。尽管对SEE故障进行建模非常关键，但集成处理器的范围使物理上正确的建模在计算上难以实现。如果没有有用的模型，就无法对容错方法进行硅前评估。为了在系统范围内纳入准确的晶体管级效应，我们提出了一种多尺度仿真框架。1）设备级别的电荷收集确定2）电路级别的瞬态持续时间和状态异常可能性。电路效应反过来会影响3）寄存器传输级别的体系结构状态损坏，在4）系统级别可见。因此，在高性能计算（HPC）仿真器上执行的大型系统中SEE的物理精确效果，通过设计可用于驱动跨层辐射硬化。我们通过两个案例研究证明了该模型的功能。首先，我们在14纳米FinFet技术上确定晶体管级D触发器的灵敏度，并根据发布的横截面验证模型。其次，我们针对各向同性空间环境中90％的最坏情况下的Adams情况，在没有互锁流水线级（MIPS）处理器的微处理器中跟踪和估计故障。