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Soft-core embedded FPGA based system on chip
Analog Integrated Circuits and Signal Processing ( IF 1.4 ) Pub Date : 2021-05-19 , DOI: 10.1007/s10470-021-01872-5
Hajer Saidi , Mariem Turki , Zied Marrakchi , Mohamed Abid , Abdulfattah Obeid

Nowadays, there has been an intensive increase in embedded systems complexity. So that optimization and performance development become an interesting topic to study. In this proposal, the main problem to solve is to make the possibility to get more flexibility, to reduce cost and to improve performance. Considering this fact, we introduce in this paper a reconfigurable component integrated into Cortex M0 based System on Chip (SoC) which has the form of embedded FPGA. To the best of our knowledge, this is the first reconfigurable SoC composed of Tree-based embedded FPGA. Besides, we explored the different ways to reach the integration and the different steps. Then, we compared reconfigurable SoC with another developed SoC which contains many hardware accelerators which are a set of popular benchmarks in terms of performance and area. Finally, we take a popular error correction algorithm “RS-Encoder” as a test case. We made the profiling of this software application in order to compare the reconfigurable SoC with a classic SoC in terms of run-time. Preliminary results were presented and showed that the eFPGA integration introduces a chip area overhead but it proves interesting results in terms of run-time. Indeed, for 100 software instructions, the eFPGA is faster 4 times compared to a hardware accelerator and 412 times compared to the software implementation of the RS Encoder application.



中文翻译:

基于软核嵌入式FPGA的片上系统

如今,嵌入式系统的复杂性已大大增加。因此,优化和性能开发成为一个有趣的研究主题。在此建议中,要解决的主要问题是使获得更大灵活性,降低成本和提高性能的可能性成为可能。考虑到这一事实,我们在本文中介绍了一种可重新配置的组件,该组件集成到基于Cortex M0的片上系统(SoC)中,具有嵌入式FPGA的形式。据我们所知,这是第一个由基于树的嵌入式FPGA组成的可重配置SoC。此外,我们探索了实现集成的不同方法以及不同的步骤。然后,我们将可重新配置的SoC与另一个开发的SoC进行了比较,该SoC包含许多硬件加速器,这些加速器是性能和面积方面的一组流行基准。最后,我们以一种流行的纠错算法“ RS-Encoder”作为测试案例。我们对该软件应用程序进行了性能分析,以便在运行时间方面将可重新配置的SoC与经典SoC进行比较。初步结果表明,eFPGA集成带来了芯片面积开销,但在运行时间方面证明了有趣的结果。实际上,对于100条软件指令,eFPGA的速度比硬件加速器快4倍,比RS编码器应用程序的软件实现快412倍。初步结果表明,eFPGA集成带来了芯片面积开销,但在运行时间方面证明了有趣的结果。实际上,对于100条软件指令,eFPGA的速度比硬件加速器快4倍,比RS编码器应用程序的软件实现快412倍。初步结果表明,eFPGA集成带来了芯片面积开销,但在运行时间方面证明了有趣的结果。实际上,对于100条软件指令,eFPGA的速度比硬件加速器快4倍,比RS编码器应用程序的软件实现快412倍。

更新日期:2021-05-19
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