With the increasing popularity and applications of 2.5-D integration, both chip and packaging industries are making significant progress in this direction. In advanced high-density 2.5-D packages, package redistribution layers become similar to chiplet back-end-of-line routing layers, and the gap between them scales down with pin density improvement. Chiplet–package interactions become significant and severely affect system performance and reliability. Moreover, 2.5-D integration offers opportunities to apply novel design techniques. The traditional die-by-die design approach neither carefully considers these interactions nor fully exploits the cross-boundary design opportunities. In this article, we present a holistic chiplet–package co-optimization flow for high-density 2.5-D packaging technologies with little performance overhead and zero pipeline-depth increase. Our holistic extraction can capture all parasitics from chiplets and the package and improve system performance through iterative optimizations. Both drop-in and pay-as-you-use design methodologies are implemented for agile development and quick turn-around time. To prove the effectiveness of our flow, we implement several design cases of a microcontroller system in TSMC 65-nm technology. Our design methodologies can reduce the performance gap by 85% with respect to the 2-D reference design after holistic optimizations. We demonstrate design flexibility and development cost-saving by presenting several flavors of a three chiplets system. To validate our flow in silicon, we tape-out a chip in TSMC 65-nm technology with measured data and validated functionality.

中文翻译：

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用于敏捷定制2.5D设计的整体小芯片-封装协同优化

随着2.5D集成的日益普及和应用，芯片和封装行业都朝着这个方向取得重大进展。在先进的高密度2.5-D封装中，封装重新分布层变得类似于小芯片后端布线层，并且它们之间的间隙随着引脚密度的提高而缩小。小芯片与封装之间的相互作用变得非常重要，并严重影响系统性能和可靠性。而且，2.5维集成为应用新颖的设计技术提供了机会。传统的逐个芯片设计方法既没有仔细考虑这些相互作用，也没有充分利用跨边界设计机会。在本文中，我们提出了针对高密度2的整体小芯片-封装协同优化流程。5-D封装技术，性能开销很小，流水线深度为零。我们的整体提取可以捕获小芯片和封装中的所有寄生虫，并通过迭代优化来改善系统性能。实施了即用型和按需使用的设计方法，以实现敏捷开发和快速的周转时间。为了证明流程的有效性，我们以台积电65纳米技术实现了微控制器系统的几个设计案例。经过整体优化后，相对于二维参考设计，我们的设计方法可以将性能差距降低85％。我们通过介绍三种小芯片系统的多种风格，展示了设计的灵活性和节省的开发成本。为了验证我们在硅片上的流程，