The apparent saturation of aggressive Moore’s law scaling of semiconductor technologies is pushing the boundaries of traditional packaging and integration schemes to accommodate the ever-growing data bandwidth and heterogeneity demands. In this article, we demonstrate the silicon-interconnect fabric (Si-IF) technology as a superior alternative to conventional printed circuit boards (PCBs) to enhance system scaling. The Si-IF is a silicon-based, package-less, fine-pitch, highly scalable, heterogeneous integration platform to assemble and integrate massive wafer-scale systems. In this technology, dielets are closely assembled on the Si-IF at small interdielet spacings ( $\leq 50~\mu \text{m}$ ) using fine-pitch ( $\leq 10~\mu \text{m}$ ) die-to-substrate interconnects allowing for tight integration on a system-level package. To achieve these fine-pitch interconnects, a novel assembly technique using solder-less direct metal–metal [copper–copper (Cu–Cu)] thermal compression bonding was developed. Using this process, sub-10- $\mu \text{m}$ -pitch interconnects with a low specific contact resistance of $\leq 0.7~\Omega \cdot \mu \text{m}~^{\mathrm{ 2}}$ and high shear force of 90 N for 4-mm ² dies were successfully demonstrated. Moreover, these fine-pitch interconnects combined with the small interdie spacing provide a large number of parallel short links ( $\leq 500~\mu \text{m}$ ) with low loss (≤2 dB) for interdielet communication that is comparable to on-chip connections. Consequently, simple buffers can transfer data between dies using a Simple Universal Parallel intERface for chips (SuperCHIPS) protocol at low link latency (<20 ps), low energy per bit (≤0.03 pJ/b), and high data rates (up to 10 Gb/s/link), corresponding to an aggregate data bandwidth of up to 8 Tb/s/mm. The benefits of the SuperCHIPS interface are experimentally demonstrated using functional dielet assembly on the Si-IF to show 4– $23\times $ higher data bandwidth, 3– $65\times $ lower latency, and 5– $40\times $ lower energy per bit compared to existing integration schemes.

中文翻译：

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细间距（≤10μm）异质集成的硅互连织物

激进的摩尔定律在半导体技术上的明显饱和正在推动传统封装和集成方案的边界，以适应不断增长的数据带宽和异构要求。在本文中，我们演示了硅互连结构（Si-IF）技术，该技术可以替代传统的印刷电路板（PCB），从而增强系统的可扩展性。Si-IF是基于硅的，无封装，小间距，高度可扩展的异构集成平台，用于组装和集成大规模晶圆级系统。在这项技术中，小晶粒以较小的小晶粒间距紧密地组装在Si-IF上（ $ \ leq 50〜\ mu \ text {m} $ ）使用小间距（ $ \ leq 10〜\ mu \ text {m} $ 管芯到基板的互连允许在系统级封装上的紧密集成。为了实现这些细间距互连，开发了一种使用无焊剂直接金属-金属[铜-铜（Cu-Cu）]热压焊的新颖组装技术。使用此过程，sub-10- $ \ mu \ text {m} $ 间距互连，具有较低的单位接触电阻 $ \ leq 0.7〜\ Omega \ cdot \ mu \ text {m}〜^ {\ mathrm {2}} $ 成功地证明了4-mm ²模具具有90 N的高剪切力。此外，这些细间距互连与较小的模间间距相结合，可提供大量的并行短链接（ $ \ leq 500〜\ mu \ text {m} $ ），具有较低的损耗（≤2dB），可用于片间通信，可与片上连接相媲美。因此，简单的缓冲器可以使用芯片的通用通用并行接口（SuperCHIPS）协议以较低的链路等待时间（<20 ps），低每位能量（≤0.03pJ / b）和高数据速率（高达10 Gb / s / link），对应于高达8 Tb / s / mm的总数据带宽。通过在Si-IF上使用功能性芯片组装实验证明了SuperCHIPS接口的优势，显示了4– $ 23 \次$ 更高的数据带宽，3 – $ 65 \次$ 较低的延迟，并且5 – $ 40 \次$ 与现有的集成方案相比，每位能耗更低。