Achieving a negative capacitance field effect transistor with a subthreshold swing beyond the Boltzmann limit requires a “defect-free” dielectric-semiconductor interface. We grew alloyed (Hf_1−xZr_xO₂) and stacked (HfO₂/ZrO₂) gate dielectrics on GaN and InP substrates using low temperature plasma enhanced atomic layer deposition. In situ ellipsometry data show that alloying hafnia with zirconia reduces the refractive index and widens the bandgap. The stacked and alloyed structures reveal very low capacitance-voltage hysteresis of 35 and 45 mV, respectively, on GaN. The density of interfacial traps as low as 1.12 × 10¹⁰ cm⁻² eV⁻¹ was achieved on GaN mainly due to the combination of very low dielectric growth temperature (100 °C) and high postfabrication heat treatment temperature (510 °C). The conduction and valence band offsets of the alloyed gate dielectrics on InP were measured and compared to pure zirconia using a combination of x-ray photoelectron spectroscopy and ellipsometry. The alloyed structures show a wider bandgap, larger conduction band offset, and smaller valence band offset compared to pure zirconia. This was attributed to the increase in the valence band width with hafnia addition, which reduces the alloyed gate dielectric’s valence band offset. We resolved the band structure alignement to be type I with band offsets of 3.53 eV for electrons and 1.03 eV for holes in Hf_0.25Zr_0.75O₂/InP heterojunctions. The results allow for a clear and detailed picture of two distinct growth procedure that affect the interfacial defect concentration.

中文翻译：

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使用在GaN和InP上的低温原子层沉积，具有极低界面缺陷密度的Hf1-xZrxO2和HfO2 / ZrO2栅电介质

要实现亚阈值摆幅超过玻尔兹曼极限的负电容场效应晶体管，需要“无缺陷”的介电半导体界面。我们使用低温等离子体增强原子层沉积技术在GaN和InP衬底上生长了合金化（Hf _1-x Zr _x O ₂）并堆叠了（HfO ₂ / ZrO ₂）栅极电介质。原位椭偏数据表明，氧化ha和氧化锆的合金化会降低折射率并扩大带隙。堆叠和合金化的结构在GaN上分别显示出非常低的35 mV和45 mV的电容电压滞后。界面陷阱的密度低至1.12×10 ¹⁰  cm ^-2  eV在GaN上实现^-1的主要原因是极低的介电层生长温度（100°C）和较高的后加工热处理温度（510°C）。测量了InP上合金化栅极电介质的导带和价带偏移，并结合使用X射线光电子能谱和椭圆偏振法将其与纯氧化锆进行了比较。与纯氧化锆相比，合金结构显示出更宽的带隙，更大的导带偏移和更小的价带偏移。这是由于添加氧化ha增加了价带宽度，从而降低了合金栅极电介质的价带偏移。我们将能带结构对准解析为I型，电子的带隙偏移为3.53 eV，空穴的带隙偏移为1.03 eV，Hf _0.25 Zr _0.75O ₂ / InP异质结。结果使影响界面缺陷浓度的两种不同的生长过程清晰明了。