Since the introduction of the CDC 6600 in 1965 and its `scoreboarding' technique processors have not (necessarily) executed instructions in program order. Programmers of high-level code may sequence independent instructions in arbitrary order, and it is a matter of significant programming abstraction and computational efficiency that the processor can be relied upon to make sensible parallelizations/reorderings of low-level instructions to take advantage of, eg., multiple ALUs. At the architectural level such reordering is typically implemented via a per-processor pipeline, into which instructions are fetched in order, but possibly committed out of order depending on local considerations, provided any reordering preserves sequential semantics from that processor's perspective. However multicore architectures, where several pipelines run in parallel, can expose these processor-level reorderings as unexpected, or `weak', behaviours. Such weak behaviours are hard to reason about, and (via speculative execution) underlie at least one class of widespread security vulnerability. In this paper we introduce a novel program operator, \emph{parallelized sequential composition}, which can be instantiated with a function that controls the reordering of atomic instructions. It generalises both sequential and parallel composition, and when appropriately instantiated exhibits many of the weak behaviours of well-known hardware weak memory models. Our framework admits the application of established compositional techniques (eg. Owicki-Gries) for reasoning about weak behaviours, and is convenient for abstractly expressing properties from the literature. The semantics and theory is encoded and verified in a theorem prover, and we give an implementation of the pipeline semantics which we use to empirically show conformance against established models of ARM and RISC-V.

中文翻译：

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并行顺序组成，流水线和硬件弱内存模型

自从1965年推出CDC 6600及其“记分板”技术以来，处理器就没有（有必要）按程序顺序执行指令。高级代码的程序员可以按任意顺序对独立的指令进行排序，并且重要的编程抽象和计算效率是可以依靠处理器对低级指令进行明智的并行化/重新排序以利用例如的优势的一个问题。 。，多个ALU。在体系结构级别上，这种重新排序通常是通过每个处理器的流水线来实现的，在该流水线中按顺序提取指令，但是可能会根据本地考虑不按顺序提交，前提是从该处理器的角度来看，任何重新排序都保留了顺序语义。但是，如果采用多核架构，多个管道并行运行的地方，可以将这些处理器级别的重新排序公开为意外或“弱”行为。这样的弱行为很难推理，并且（通过推测执行）是至少一类广泛的安全漏洞的基础。在本文中，我们介绍了一种新颖的程序运算符\ emph {parallelized sequence composition}，可以使用控制原子指令重新排序的函数来实例化该程序。它概括了顺序和并行组合，并在适当实例化时表现出许多众所周知的硬件弱存储器模型的弱行为。我们的框架允许使用已建立的合成技术（例如Owicki-Gries）来对弱行为进行推理，并且便于从文献中抽象表达特性。