The quest for the high speed, low power digital logic circuits urge an imperative demand of compatible high-κ dielectric integration on novel Germanium (Ge) based channel material. Here, first ever a methodical nanoscopic and microscopic probes were attempted to Atomic Layer Deposited, Hafnium Dioxide (HfO ₂ ) dielectrics on Molecular Beam Epitaxy (MBE) of p-Ge _-on- p-Si stack. Kelvin Probe Force Microscopy based contact potential difference (CPD) analysis reveals that the disintegration of trapped charges lasting for ∼18 hours. The impact of constant voltage stress (CVS) on trapped charges results in variation of threshold voltage (V _th ) and hysteresis window (W) were studied. The cyclic Capacitance-Voltage (C-V) characteristics at 0.5 MHz exhibit the shift in the flat band (ΔV _fb ), ΔV _th , and ΔW at 10V stress were ∼0.84V, ∼0.62V, and ∼0.47V, respectively. While the computed interface trap density (D _it ) and total effective charge density (Q _eff ) were ∼8.49 × 10 ¹² eV ⁻¹ cm ⁻² and ∼1.81 × 10 ¹² cm ⁻² _, respectively. The gate leakage current density, (J) at 5V is 26.53 × 10 ⁻⁶ A/cm ² and reduced by a factor of ∼6.8 after 10V, CVS. Whereas the current density (J) increases from ∼26.53 × 10 ⁻⁶ A/cm ² at 25 °C by a factor of ∼2 at 125 °C. To study the retention and effect of charge trapping, the stress-time analysis was performed for 8000s at 3V (CVS). The r.m.s. surface roughness of HfO ₂ thin films was found to be ∼0.23 nm. X-ray photoelectron spectroscopy (XPS) depth profiling categorized the elemental composition of thin films. These investigations would help to HfO ₂ /p-Ge _-on- p-Si system interfacial engineering well before the Ge based nano device realization.

中文翻译：

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电荷捕获上的外延对葛的影响_-ON-的p-Si和HFO ₂ Al系/的HfO ₂ / P-戈_-ON-的p-Si /铝结构采用开尔文探针力显微镜和恒定电压应力

对高速，低功耗数字逻辑电路的追求，迫切要求在新型锗（Ge）基沟道材料上实现兼容的高k电介质集成。在此，第一次有条不紊纳米级和显微镜探针尝试原子层沉积，二氧化铪（HFO ₂ ）在p锗的分子束外延（MBE）的电介质 _-ON- 的p-Si叠层。基于开尔文探针力显微镜的接触电势差（CPD）分析表明，捕获电荷的崩解持续约18小时。恒定电压应力（CVS）对俘获电荷的影响导致阈值电压（V _th ）和滞后窗（W）进行了研究。环状电容-电压（CV）特性中的0.5兆赫表现出在平带（ΔV移位 _FB ），ΔV _个 ，和ΔW在10V应力分别~0.84V，~0.62V，和~0.47V，分别。而计算出的界面陷阱密度（d _它 ）和总有效电荷密度（Q _EFF ）为~8.49×10 ¹²电子伏特 ^-1 厘米 ^-2和~1.81×10 ¹²厘米 ^-2 _，分别。5V时的栅极泄漏电流密度（J）为26.53×10 ^-6 A / cm ²CVS在10V后降低约6.8倍。而电流密度（J）在25°C时从〜26.53×10 ^-6 A / cm ²增加到125°C时的〜2倍 。为了研究电荷陷阱的保留和影响，在3V（CVS）下进行了8000s的应力时间分析。发现HfO ₂薄膜的均方根表面粗糙度 约为0.23 nm。X射线光电子能谱（XPS）深度分析对薄膜的元素组成进行了分类。这些研究将有助于 在基于Ge的纳米器件实现之前HfO ₂ / p-Ge- _on -p-Si系统界面工程。