Electronic railway interlockings are critical embedded systems which control the safe operation of train signals. Due to the broad variety of railway network topologies and the high functional safety level required, a flexible solution is needed, capable of taking formal requirements and implementing them accordingly to the required application. The scope of this work is to present an approach in which an automatic code generator transforms the control tables which describe the interlocking logic into functional units written in different programming languages like C or VHDL. The generated code allows its implementation in an embedded system based in a FPGA or a microcontroller. In addition, the project contains a graphical user interface to draw and simulate the behavior of the generated model for verification purposes. The developed tool comprises the entire design flow for interlocking systems and presentes several advantages when compared to previous works.

中文翻译：

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电子铁路联锁系统的建模，仿真和代码生成

电子铁路联锁系统是控制火车信号安全运行的关键嵌入式系统。由于铁路网络拓扑结构的多样性和所需的高功能安全性，因此需要一种灵活的解决方案，该解决方案能够满足正式的要求并根据所需的应用程序对其进行实施。这项工作的范围是提出一种方法，其中自动代码生成器将描述互锁逻辑的控制表转换为以不同编程语言（如C或VHDL）编写的功能单元。生成的代码允许其在基于FPGA或微控制器的嵌入式系统中实现。此外，该项目还包含一个图形用户界面，以绘制和模拟所生成模型的行为以进行验证。