This paper introduces a novel framework that automates and accelerates the development of embedded Field Programmable Gate Arrays (eFPGAs). The proposed solution is considered as the first environment for tree-based eFPGA implementation including software, hardware and loader. The developed framework allows users to generate eFPGA architecture in the form of hardware description language using Physical Design Flow (PDF) tool. It is a powerful tool that can produce a wide variety of designs ranging from small eFPGA to complex eFPGA. The bit file description of practical application is done in parallel, simultaneously and rapidly by the suggested Computer Aided Design (CAD) tools. The Loader, called Multi-Level Loader (MLL), is also provided to inject the bits into the corresponding SRAMs. Our framework is widely explored by modifying the data width. This research proves that data width equal to 17 has the best trade-off between performance, area and static power. However, it is penalized for buses having data length greater than 32. The experimentation demonstrates that a data width equal to 12 is the best for a 32-bit bus. Automation and significant acceleration of the eFPGA development cycle are also achieved in this study. A set of bench-marking applications with various multi-use purposes is mapped. The experimental results show the efficiency and flexibility of the proposed framework.

中文翻译：

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使用自动化框架探索基于树的嵌入式 FPGA 上的字宽和簇大小影响

本文介绍了一种新颖的框架，该框架可自动化并加速嵌入式现场可编程门阵列 (eFPGA) 的开发。所提出的解决方案被认为是基于树的 eFPGA 实现的第一个环境，包括软件、硬件和加载器。开发的框架允许用户使用物理设计流程 (PDF) 工具以硬件描述语言的形式生成 eFPGA 架构。它是一个强大的工具，可以生成从小型 eFPGA 到复杂 eFPGA 的各种设计。实际应用的位文件描述是由建议的计算机辅助设计 (CAD) 工具并行、同时和快速完成的。还提供了称为多级加载器 (MLL) 的加载器，用于将位注入相应的 SRAM。我们的框架通过修改数据宽度得到了广泛的探索。这项研究证明，数据宽度等于 17 在性能、面积和静态功耗之间具有最佳平衡。但是，对于数据长度大于 32 的总线，它会受到惩罚。实验表明，对于 32 位总线来说，数据宽度等于 12 是最好的。本研究还实现了 eFPGA 开发周期的自动化和显着加速。映射了一组具有各种多用途用途的基准测试应用程序。实验结果表明了所提出框架的效率和灵活性。本研究还实现了 eFPGA 开发周期的自动化和显着加速。映射了一组具有各种多用途用途的基准测试应用程序。实验结果表明了所提出框架的效率和灵活性。本研究还实现了 eFPGA 开发周期的自动化和显着加速。映射了一组具有各种多用途用途的基准测试应用程序。实验结果表明了所提出框架的效率和灵活性。