This paper presents a novel low-leakage 10T SRAM cell along with its new read circuitry. It utilizes isolated read path for the read operation that enhances the read stability of the cell as compared to conventional 6T SRAM cell. The proposed cell has been introduced for IoT applications where low power devices are the primary requirement in order to enhance the battery life. To minimize the leakage current, the PMOS transistor has been employed at the read circuitry which assists to minimize the leakage current due to induced stacking effect. The leakage current is 37.66%, 40.11% and 67.39% less as compared to 6T SRAM, 8T SRAM and RDPFC 9T SRAM cells, respectively. The read delay for the proposed cell is 39.80%, 89.13% and 42.33% less as compared to 6T SRAM, 8T SRAM and RDPFC 9T SRAM cells, respectively. Also, the results depict the speed improvement of 48.60%, 52.49% and 55.71% during write “0” and 46.97%, 57.5% and 54.52% improvement during write “1” operation as compared to 6T SRAM, 8T SRAM and RDFC 9T SRAM cells, respectively. The RSNM of the proposed cell is 649 mV that shows enhanced read stability over conventional 6T SRAM cell. The proposed cell proves its robustness against worst-case process variations. All the simulation work has been completed on the Cadence Virtuoso environment at 180 nm technology node.

中文翻译：

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用于物联网应用的低泄漏变化感知 10T SRAM 单元

本文介绍了一种新型低泄漏 10T SRAM 单元及其新的读取电路。它利用隔离的读取路径进行读取操作，与传统的 6T SRAM 单元相比，提高了单元的读取稳定性。所提出的电池已被引入物联网应用，其中低功率设备是延长电池寿命的主要要求。为了最大限度地减少泄漏电流，PMOS 晶体管已用于读取电路，这有助于最大限度地减少由于感应堆叠效应引起的泄漏电流。与 6T SRAM、8T SRAM 和 RDPFC 9T SRAM 单元相比，漏电流分别减少了 37.66%、40.11% 和 67.39%。与 6T SRAM、8T SRAM 和 RDPFC 9T SRAM 单元相比，该单元的读取延迟分别减少了 39.80%、89.13% 和 42.33%。还，结果显示，与 6T SRAM、8T SRAM 和 RDFC 9T SRAM 单元相比，写“0”期间的速度提高了 48.60%、52.49% 和 55.71%，而写“1”操作期间的速度提高了 46.97%、57.5% 和 54.52%，分别。所提议单元的 RSNM 为 649 mV，与传统的 6T SRAM 单元相比，显示出更高的读取稳定性。所提出的单元证明了其对最坏情况工艺变化的鲁棒性。所有的仿真工作已经在 Cadence Virtuoso 环境中以 180 nm 技术节点完成。所提出的单元证明了其对最坏情况工艺变化的鲁棒性。所有的仿真工作已经在 Cadence Virtuoso 环境中以 180 nm 技术节点完成。所提出的单元证明了其对最坏情况工艺变化的鲁棒性。所有的仿真工作已经在 Cadence Virtuoso 环境中以 180 nm 技术节点完成。