This brief presents a second-order discrete-time (DT) modified feed-forward (FF) delta-sigma modulator. To reduce the attenuation of the quantizer’s input signal due to switched-capacitor (SC) passive summing, the proposed modulator eliminates the internal FF path and reduces the number of input signals of the adder. A 4-bit asynchronous successive-approximation-register (SAR) analog-to-digital converter (ADC) incorporated with a passive adder is used to reduce power consumption and area. To allow the conversion delay of the SAR ADC, a delayed feedback is adopted. The prototype ADC is fabricated in a $0.11~\mu \text{m}$ CMOS process using four metal layers with an active die area of 0.165mm ² . It achieves a dynamic range (DR) of 96.3 dB and a peak signal-to-noise and distortion ratio (SNDR) of 93.9 dB in a 2 kHz signal bandwidth while consuming $62.43~\mu \text{W}$ from a 1.8V/1.65V power supply, corresponding to a Schreier figure-of-merit (FOM) of 171dB.

中文翻译：

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使用改进的前馈架构和延迟反馈的96dB动态范围2kHz带宽二阶Delta-Sigma调制器

本简介介绍了一个二阶离散时间（DT）修改的前馈（FF）Δ-Σ调制器。为了减少由于开关电容器（SC）无源求和引起的量化器输入信号的衰减，建议的调制器消除了内部FF路径并减少了加法器的输入信号数量。集成有无源加法器的4位异步逐次逼近寄存器（SAR）模数转换器（ADC）用于降低功耗和面积。为了允许SAR ADC的转换延迟，采用了延迟反馈。ADC原型是在一个 $ 0.11〜\ mu \ text {m} $ 使用活动裸片面积为0.165mm ^2的四个金属层的CMOS工艺 。它在2 kHz的信号带宽中实现了96.3 dB的动态范围（DR）和93.9 dB的峰值信噪比和失真比（SNDR），同时消耗了 $ 62.43〜\ mu \ text {W} $ 由1.8V / 1.65V电源供电，对应于171dB的Schreier品质因数（FOM）。