Stochastic Computing (SC) is a computing paradigm that allows for the low-cost and low-power computation of various arithmetic operations using stochastic bit streams and digital logic. In contrast to conventional representation schemes used within the binary domain, the sequence of bit streams in the stochastic domain is inconsequential, and computation is usually non-deterministic. In this brief, we exploit the stochasticity during switching of probabilistic Conductive Bridging RAM (CBRAM) devices to efficiently generate stochastic bit streams in order to perform Deep Learning (DL) parameter optimization, reducing the size of Multiply and Accumulate (MAC) units by 5 orders of magnitude. We demonstrate that in using a 40-nm Complementary Metal Oxide Semiconductor (CMOS) process our scalable architecture occupies 1.55mm ² and consumes approximately $167~\mu \text{W}$ when optimizing parameters of a Convolutional Neural Network (CNN) while it is being trained for a character recognition task, observing no notable reduction in accuracy post-training.

中文翻译：

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忆阻随机计算用于深度学习参数优化

随机计算（SC）是一种计算范例，它允许使用随机位流和数字逻辑对各种算术运算进行低成本和低功耗的计算。与在二进制域中使用的常规表示方案相比，随机域中的位流顺序是无关紧要的，并且计算通常是不确定的。在本简介中，我们利用概率导电桥接RAM（CBRAM）器件切换期间的随机性来有效地生成随机位流，以执行深度学习（DL）参数优化，从而将乘加和累加（MAC）单元的大小减少了5数量级。我们证明，在使用40nm互补金属氧化物半导体（CMOS）工艺时，我们的可扩展架构占用1.55mm ² 大约消耗 $ 167〜\ mu \ text {W} $ 在针对字符识别任务进行训练时优化卷积神经网络（CNN）的参数时，观察到的训练后准确性没有明显降低。