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A 9.8–30.1 GHz CMOS low-noise amplifier with a 3.2-dB noise figure using inductor- and transformer-based g m -boosting techniques
Frontiers of Information Technology & Electronic Engineering ( IF 3 ) Pub Date : 2021-05-02 , DOI: 10.1631/fitee.2000510
Hongchen Chen , Haoshen Zhu , Liang Wu , Wenquan Che , Quan Xue

A 9.8–30.1 GHz CMOS low-noise amplifier (LNA) with a 3.2-dB minimum noise figure (NF) is presented. At the architecture level, a topology based on common-gate (CG) cascading with a common-source (CS) amplifier is proposed for simultaneous wideband input matching and relatively high gain. At the circuit level, multiple techniques are proposed to improve LNA performance. First, in the CG stage, loading effect is properly used instead of the conventional feedback technique, to enable simultaneous impedance and noise matching. Second, based on in-depth theoretical analysis, the inductor- and transformer-based gm-boosting techniques are employed for the CG and CS stages, respectively, to enhance the gain and reduce power consumption. Third, the floating-body method, which was originally proposed to lower NF in CS amplifiers, is adopted in the CG stage to further reduce NF. Fabricated in a 65-nm CMOS technology, the LNA chip occupies an area of only 0.2 mm2 and measures a maximum power gain of 10.9 dB with −3 dB bandwidth from 9.8 to 30.1 GHz. The NF exhibits a minimum value of 3.2 dB at 15 GHz and is below 5.7 dB across the entire bandwidth. The LNA consumes 15.6 mW from a 1.2-V supply.



中文翻译:

使用基于电感器和变压器的gm增强技术,具有3.2dB噪声系数的9.8-30.1 GHz CMOS低噪声放大器

给出了具有3.2dB最小噪声系数(NF)的9.8-30.1 GHz CMOS低噪声放大器(LNA)。在体系结构级别上,提出了一种基于共栅(CG)与共源(CS)放大器级联的拓扑结构,用于同时进行宽带输入匹配和相对较高的增益。在电路级,提出了多种技术来提高LNA性能。首先,在CG阶段,适当使用负载效应代替了传统的反馈技术,以实现同时的阻抗和噪声匹配。其次,基于深入的理论分析,基于电感和变压器的g m升压技术分别用于CG和CS级,以增强增益并降低功耗。第三,CG阶段采用了浮体法,最初是为了降低CS放大器中的NF而提出的,以进一步降低NF。LNA芯片采用65 nm CMOS技术制造,仅占0.2 mm 2的面积,在9.8至30.1 GHz的−3 dB带宽下,最大功率增益为10.9 dB。在15 GHz时,NF的最小值为3.2 dB,在整个带宽上均低于5.7 dB。LNA从1.2V电源消耗15.6mW的功率。

更新日期:2021-05-03
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