The integration of FPGA-based accelerators into a complete heterogeneous system is a challenging task faced by many researchers and engineers, especially now that FPGAs enjoy increasing popularity as implementation platforms for efficient, application-specific accelerators for domains such as signal processing, machine learning and intelligent storage. To lighten the burden of system integration from the developers of accelerators, the open-source TaPaSCo framework presented in this work provides an automated toolflow for the construction of heterogeneous many-core architectures from custom processing elements, and a simple, uniform programming interface to utilize spatially distributed, parallel computation on FPGAs. TaPaSCo aims to increase the scalability and portability of FPGA designs through automated design space exploration, greatly simplifying the scaling of hardware designs and facilitating iterative growth and portability across FPGA devices and families. This work describes TaPaSCo with its primary design abstractions and shows how TaPaSCo addresses portability and extensibility of FPGA hardware designs for systems-on-chip. A study of successful projects using TaPaSCo shows its versatility and can serve as inspiration and reference for future users, with more details on the usage of TaPaSCo presented in an in-depth case study and a short overview of the workflow.

将基于FPGA的加速器集成到完整的异构系统中是许多研究人员和工程师面临的一项艰巨任务，尤其是当FPGA作为针对诸如信号处理，机器学习和计算机应用等领域的高效，专用加速器的实现平台而日益普及时，尤其如此。智能存储。为了减轻加速器开发人员的系统集成负担，本工作中介绍的开源TaPaSCo框架提供了一种自动工具流，用于从自定义处理元素构建异构多核体系结构，并提供了一个简单，统一的编程接口以供使用FPGA上的空间分布式并行计算。TaPaSCo旨在提高可扩展性和通过自动设计空间探索，FPGA设计具有可移植性，从而大大简化了硬件设计的规模，并促进了FPGA设备和系列之间的迭代增长和可移植性。这项工作描述了TaPaSCo及其主要设计抽象，并展示了TaPaSCo如何解决片上系统的FPGA硬件设计的可移植性和可扩展性。对使用TaPaSCo的成功项目的研究显示了它的多功能性，可以作为未来用户的灵感和参考，在深入的案例研究和工作流的简要概述中提供了有关TaPaSCo用法的更多详细信息。