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A Conversion Mode Reconfigurable SAR ADC for Multistandard Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems ( IF 2.8 ) Pub Date : 2021-03-02 , DOI: 10.1109/tvlsi.2021.3059857
Jian Liu , Shubin Liu , Ruixue Ding , Zhangming Zhu

A single-channel reconfigurable successive approximation register (SAR) analog-to-digital converter (ADC) is presented, which features its speed expanding with conversion mode. The reconfigurable capacitor digital to analog converter (CDAC) is proposed to achieve multiple conversion modes without wasting capacitance. In 1-b/cycle conversion mode, the proposed ADC can achieve the sampling rate of 60-Ms/s and 9-b resolution. Based on the 2-b/cycle conversion mode, the proposed ADC can double the sampling rate and be reconfigured as a 120-MS/s, 8-b converter. Besides, the detection skip algorithm and charge sharing technology are involved to remove the precharge operation time and reduce the switching energy consumption. Moreover, the control logic is optimized to minimize the chip area and matches the reconfigurable characteristics well. A prototype ADC is fabricated in the 180-nm standard CMOS process, which achieves the 54.1-/46.7-dB signal-to-noise-plus-distortion ratio (SNDR) at 60-/120-MHz sampling frequency with the power consumption of 1.9/3.5 mW. The prototype ADC achieves a peak figure of merit (FoM) of 77-fJ/Conv.step at 2-b/cycle conversion mode. The ADC core occupies an active area of only 0.12 mm 2 .

中文翻译:

适用于多标准系统的转换模式可重配置SAR ADC

提出了一种单通道可重构逐次逼近寄存器(SAR)模数转换器(ADC),其功能随着转换模式而扩展。提出了可重构电容器的数模转换器(CDAC),以实现多种转换模式而不会浪费电容。在1b /周期转换模式下,建议的ADC可以实现60-Ms / s的采样率和9b的分辨率。基于2-b /周期转换模式,建议的ADC可以将采样率提高一倍,并可以重新配置为120-MS / s的8-b转换器。此外,还涉及检测跳过算法和电荷共享技术,以消除预充电操作时间并减少开关能量消耗。此外,优化了控制逻辑以最大程度地减少芯片面积并很好地匹配可重新配置的特性。ADC原型是在180nm标准CMOS工艺中制造的,在60- / 120MHz的采样频率下,其信噪比和失真比(SNDR)达到54.1- / 46.7dB,功耗为1.9 / 3.5毫瓦。原型ADC在2b /周期转换模式下的峰值品质因数(FoM)为77-fJ / Conv.step。ADC内核仅占用0.12 mm的有效面积 2
更新日期:2021-04-30
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