In this article, a static frequency divider based on folded MOS current mode logic (FMCML) is presented. The design is based on alternating FMCML flip-flops with complementary pMOS or nMOS input differential pairs since common-mode problems arise by using only one type of FMCML flip-flops. The design is carried out after detailed theoretical modeling and analysis versus the flip-flop bias current, thus allowing defining optimized design strategies for the maximum speed or the minimum power-delay product (PDP). The frequency divider architecture and design strategies are validated considering a commercial 28-nm FDSOI CMOS technology. Postlayout simulations of a divider-by-16 show a maximum frequency of about 12 GHz with 74- $\mu \text{W}$ power consumption for the high-speed design and a maximum frequency of 10 GHz with 53- $\mu \text{W}$ power consumption for the minimum PDP design.

中文翻译：

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具有互补n型和p型触发器的折叠MOS电流模式逻辑中的超低电压分频器

在本文中，提出了一种基于折叠式MOS电流模式逻辑（FMCML）的静态分频器。该设计基于具有互补pMOS或nMOS输入差分对的交替FMCML触发器，因为共模问题仅通过使用一种FMCML触发器而出现。设计是在详细的理论建模和分析之后，再针对触发器偏置电流进行的，因此可以为最大速度或最小功率延迟乘积（PDP）定义优化的设计策略。考虑了商用28纳米FDSOI CMOS技术，验证了分频器架构和设计策略。16分频器的布局后仿真显示，最大频率约为12 GHz，其中74- $ \ mu \ text {W} $ 高速设计的功耗，最大频率为10 GHz（53- $ \ mu \ text {W} $ 最小PDP设计的功耗。