This paper presents a quaternary latch and two edge-sensitive quaternary flip-flops (QFFs), which are capable of storing a quaternary digit. Two complementary outputs are often generated in a flip-flop inevitably. However, the new designs offer the opportunity to eliminate one of the quaternary outputs with the aim of area and static power reduction. This feature reduces the number of transistors by four and cuts static power dissipation by 47.5% when resistive voltage dividers are used. Simulation results show promising outcomes for the proposed QFFs, which are based on CMOS technology and a single power supply. They provide an excellent compromise between the delay and power factors in comparison with the previous CMOS and CNFET QFFs. The first proposed design with resistive voltage dividers, Design #1, operates with 70.96% and 38.19% lower power-delay product (PDP) than the earlier QFFs with the fastest speed and the lowest power consumption, respectively. The second one with capacitive voltage dividers, Design #2, avoids continuous static current during the production of logic values ‘1’ and ‘2’ and improves PDP even more significantly. Setup time, hold time, critical clock skew, and robustness against process, voltage, and temperature (PVT) variations are also measured showing considerable improvements compared to the previous designs. Finally, the applicability and correct functionality of the proposed QFFs in larger sequential circuits is verified by designing a quaternary shift register and a quaternary decrementing counter.

本文提出了一个四进制锁存器和两个边沿敏感的四进制触发器（QFF），它们能够存储一个四进制数字。通常会在触发器中不可避免地产生两个互补输出。但是，新设计为消除面积和静态功耗的目的而提供了消除四元输出之一的机会。使用电阻分压器时，此功能可将晶体管数量减少四个，并将静态功耗降低47.5％。仿真结果表明，所提出的基于CMOS技术和单电源的QFF的结果令人鼓舞。与以前的CMOS和CNFET QFF相比，它们在延迟和功率因数之间提供了出色的折衷方案。提出的第一个带有电阻分压器的设计（设计＃1）的工作效率为70.96％和38。与早期的QFF相比，功率延迟产品（PDP）的速度和速度分别比最快的速度和最低的功耗低19％。第二个具有电容性分压器的设计＃2避免了在产生逻辑值“ 1”和“ 2”时产生连续的静态电流，并显着提高了PDP。还测量了建立时间，保持时间，关键时钟偏斜以及针对过程，电压和温度（PVT）变化的鲁棒性，与以前的设计相比，显示出显着的改进。最后，通过设计四进制移位寄存器和四进制递减计数器，验证了所提出的QFF在较大的时序电路中的适用性和正确的功能。第二个具有电容性分压器的设计（设计2）避免了在产生逻辑值“ 1”和“ 2”时产生连续的静态电流，并显着提高了PDP。还测量了建立时间，保持时间，关键时钟偏斜以及针对过程，电压和温度（PVT）变化的鲁棒性，与以前的设计相比，显示出显着的改进。最后，通过设计四进制移位寄存器和四进制递减计数器，验证了所提出的QFF在较大的时序电路中的适用性和正确的功能。第二个具有电容性分压器的设计＃2避免了在产生逻辑值“ 1”和“ 2”时产生连续的静态电流，并显着提高了PDP。还测量了建立时间，保持时间，关键时钟偏斜以及针对过程，电压和温度（PVT）变化的鲁棒性，与以前的设计相比，显示出显着的改进。最后，通过设计四进制移位寄存器和四进制递减计数器，验证了所提出的QFF在较大的时序电路中的适用性和正确的功能。还测量了温度（PVT）的变化，与以前的设计相比，显示出显着的改进。最后，通过设计四进制移位寄存器和四进制递减计数器，验证了所提出的QFF在较大的时序电路中的适用性和正确的功能。还测量了温度（PVT）的变化，与以前的设计相比，显示出显着的改进。最后，通过设计四进制移位寄存器和四进制递减计数器，验证了所提出的QFF在较大的时序电路中的适用性和正确的功能。