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A Full-Duplex Receiver With True-Time-Delay Cancelers Based on Switched-Capacitor-Networks Operating Beyond the Delay–Bandwidth Limit
IEEE Journal of Solid-State Circuits ( IF 5.4 ) Pub Date : 2021-03-15 , DOI: 10.1109/jssc.2021.3063658
Aravind Nagulu , Aditya Gaonkar , Sohail Ahasan , Sasank Garikapati , Tingjun Chen , Gil Zussman , Harish Krishnaswamy

Wideband self-interference cancellation (SIC) in full-duplex (FD) radios requires the achievement of large delays to accurately emulate the SI channel. However, compact, power-efficient, low-loss/noise/distortion nanosecond-scale delays are extremely challenging to achieve on silicon. Passive transmission lines on silicon are lossy and area-intensive and exhibit reduced bandwidths when miniaturized using inductors and capacitors, whereas active approaches are noisy and power-hungry. In this work, we present a technique that leverages switched-capacitor circuits with multiphase clocking to obtain large on-chip delays over wide bandwidths with the low area and power consumption, thus exceeding the delay–bandwidth product (DBW) limits offered by conventional linear time-invariant (LTI) circuits. This technique is demonstrated in an FD receiver with time-interleaved switched-capacitor-based delay cells in RF and BB domains. The FD receiver is implemented in a standard 65-nm CMOS process and operates from 100 MHz–1 GHz with gain tunability of 15–38 dB, a noise figure of 5.4 dB, and power consumption of 31 mW. The RF/BB canceler delay cells have real-/complex-valued weighting with delays ranging from 0.2–1.1 ns/10–75 ns while consuming 25.5 and 6.5 mW, respectively. These large tunable delays perform FIR-filtering-based cancellation, enabling 30–35-dB integrated SI cancellation over 20 MHz on top of an off-the-shelf ferrite circulator when terminated by a dipole antenna (isolation of 22 dB), and can handle TX power of up to +9 dBm. Under SIC, the RF and BB cancelers degrade the RX noise figure by 1.1 and 0.8 dB, respectively.

中文翻译:

基于具有超过延迟带宽限制的开关电容器网络的,具有实时延时消除器的全双工接收器

全双工(FD)无线电中的宽带自干扰消除(SIC)需要实现较大的延迟才能准确模拟SI信道。然而,在硅上实现紧凑,省电,低损耗/噪声/失真纳秒级延迟极具挑战性。硅上的无源传输线有损且面积大,并且使用电感器和电容器将其小型化时,带宽会减小,而有源方法会产生噪声且耗电。在这项工作中,我们提出一种利用开关电容器电路和多相时钟的技术,以较低的面积和功耗在宽带宽上获得较大的片上延迟,从而超过传统线性放大器提供的延迟带宽乘积(DBW)限制。时不变(LTI)电路。在FD接收器中演示了此技术,该接收器在RF和BB域中具有基于时间交织的基于开关电容器的延迟单元。FD接收器以标准的65纳米CMOS工艺实现,工作频率为100 MHz–1 GHz,增益可调性为15–38 dB,噪声系数为5.4 dB,功耗为31 mW。RF / BB抵消器延迟单元具有实/复值加权,延迟范围为0.2–1.1 ns / 10–75 ns,分​​别消耗25.5和6.5 mW。这些大的可调谐延迟执行基于FIR滤波的消除,当由偶极天线终止时(隔离度为22 dB),可以在现成的铁氧体环行器之上在20 MHz上实现30–35 dB的集成SI消除,并且可以处理高达+9 dBm的TX功率。在SIC下,RF和BB消除器分别使RX噪声系数降低1.1和0.8 dB。
更新日期:2021-04-27
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