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Design Automation for Tree-based Nearest Neighborhood–aware Placement of High-speed Cellular Automata on FPGA with Scan Path Insertion
ACM Transactions on Design Automation of Electronic Systems ( IF 1.4 ) Pub Date : 2021-04-23 , DOI: 10.1145/3446206
Ayan Palchaudhuri 1 , Sandeep Sharma 1 , Anindya Sundar Dhar 1
Affiliation  

Cellular Automata (CA) is attractive for high-speed VLSI implementation due to modularity, cascadability, and locality of interconnections confined to neighboring logic cells. However, this outcome is not easily transferable to tree-structured CA, since the neighbors having half and double the index value of the current CA cell under question can be sufficiently distanced apart on the FPGA floor. Challenges to meet throughput requirements, seamlessly translate algorithmic modifications for changing application specifications to gate level architectures and to address reliability challenges of semiconductor chips are ever increasing. Thus, a proper design framework assisting automation of synthesizable, delay-optimized VLSI architecture descriptions facilitating testability is desirable. In this article, we have automated the generation of hardware description of tree-structured CA that includes a built-in scan path realized with zero area and delay overhead. The scan path facilitates seeding the CA, state modification, and fault localization on the FPGA fabric. Three placement algorithms were proposed to ensure maximum physical adjacency amongst neighboring CA cells, arranged in a multi-columnar fashion on the FPGA grid. Our proposed architectures outperform implementations arising out of standard placers and behavioral designs, existing tree mapping strategies, and state-of-the-art FPGA centric error detection architectures in area and speed.

中文翻译:

基于树的最近邻域感知高速元胞自动机在 FPGA 上的设计自动化与扫描路径插入

元胞自动机 (CA) 因其模块化、级联性和仅限于相邻逻辑单元的互连的局部性而对高速 VLSI 实施具有吸引力。然而,这个结果不容易转移到树形结构 CA,因为具有当前所讨论的当前 CA 单元的一半和两倍索引值的邻居可以在 FPGA 地板上相距足够远。满足吞吐量要求、将不断变化的应用规范的算法修改无缝转换为门级架构以及解决半导体芯片的可靠性挑战的挑战正在不断增加。因此,需要一个适当的设计框架来辅助可综合的、延迟优化的 VLSI 架构描述的自动化,从而促进可测试性。在本文中,我们已经自动生成树结构 CA 的硬件描述,其中包括以零面积和延迟开销实现的内置扫描路径。扫描路径有助于在 FPGA 架构上播种 CA、状态修改和故障定位。提出了三种布局算法,以确保相邻 CA 单元之间的最大物理邻接,在 FPGA 网格上以多列方式排列。我们提出的架构在面积和速度方面优于标准布局器和行为设计、现有树映射策略以及最先进的以 FPGA 为中心的错误检测架构所产生的实现。和 FPGA 架构上的故障定位。提出了三种布局算法,以确保相邻 CA 单元之间的最大物理邻接,在 FPGA 网格上以多列方式排列。我们提出的架构在面积和速度方面优于标准布局器和行为设计、现有树映射策略以及最先进的以 FPGA 为中心的错误检测架构所产生的实现。和 FPGA 架构上的故障定位。提出了三种布局算法,以确保相邻 CA 单元之间的最大物理邻接,在 FPGA 网格上以多列方式排列。我们提出的架构在面积和速度方面优于标准布局器和行为设计、现有树映射策略以及最先进的以 FPGA 为中心的错误检测架构所产生的实现。
更新日期:2021-04-23
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