Highly dependable communication networks usually rely on some kind of Fast Re-Route (FRR) mechanism which allows to quickly re-route traffic upon failures, entirely in the data plane. This paper studies the design of FRR mechanisms for emerging reconfigurable switches. Our main contribution is an FRR primitive for programmable data planes, PURR, which provides low failover latency and high switch throughput, by avoiding packet recirculation . PURR tolerates multiple concurrent failures and comes with minimal memory requirements, ensuring compact forwarding tables, by unveiling an intriguing connection to classic “string theory” ( i.e. , stringology), and in particular, the shortest common supersequence problem. PURR is well-suited for high-speed match-action forwarding architectures ( e.g. , PISA) and supports the implementation of a broad variety of FRR mechanisms. Our simulations and prototype implementation (on an FPGA and a Tofino switch) show that PURR improves TCAM memory occupancy by a factor of $1.5 \times$ – $10.8 \times$ compared to a naïve encoding when implementing state-of-the-art FRR mechanisms. PURR also improves the latency and throughput of datacenter traffic up to a factor of $2.8 \times$ – $5.5 \times$ and $1.2 \times$ – $2 \times$ , respectively, compared to approaches based on recirculating packets.

中文翻译：

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可编程交换机上的快速重路由

高度可靠的通信网络通常依赖某种快速重路由（FRR）机制，该机制可在发生故障时快速将流量完全重新路由到数据平面中。本文研究了新兴可重配置交换机的FRR机制的设计。我们的主要贡献是FRR原语用于可编程的 数据平面PURR，可通过以下方式提供低故障切换延迟和高交换吞吐量 避免数据包循环 。PURR可以容忍多个并发故障，并具有最小的内存要求，从而确保袖珍的 通过揭示与经典“弦论”的有趣联系来转发表（ IE （字符串学），尤其是最短的常见超序列问题。PURR非常适合高速匹配动作转发架构（ 例如 （PISA），并支持各种FRR机制的实施。我们的仿真和原型实现（在FPGA和Tofino开关上）表明，PURR将TCAM存储器的占用率提高了近一倍。 $ 1.5 \次 – $ 10.8 \次$ 与实施最新的FRR机制时的简单编码相比。PURR还可以将数据中心流量的延迟和吞吐量提高多达一个因素。 $ 2.8 /次 – $ 5.5 \次$ 和 $ 1.2 \次 – $ 2 \次 分别与基于循环数据包的方法进行了比较。