Flip-flops (FFs) account for a very significant portion of the entire power consumption of VLSI circuits. Magnetic tunnel junctions (MTJs) can be combined with conventional FFs to achieve nonvolatility, almost unlimited write times, and higher energy efficiency. The mainstream MTJ switching mechanisms include spin-transfer torque (STT), spin-orbit torque (SOT), and voltage-controlled magnetic anisotropy (VCMA) effect, among them the first two mechanisms all facing the disadvantages of both large writing energy and writing latency. Instead, utilizing the VCMA effect to switch MTJ only needs a sub-nanosecond and has low energy consumption, which is more energy-efficient. In this article, first, a double-stage pre-charge sense amplifier (DPCSA) is proposed, reducing 53.9% of sensing delay compared with the conventional one. Second, based on DPCSA, a VCMA-MTJ-based multi-bit shared magnetic nonvolatile FF (MNV-FF) with a self-adaptive writing circuit is designed, achieving high speed and energy efficiency for backup and restore operations. Finally, by extending the MNV-FF, a magnetic nonvolatile register group (MNV-RG) with high area efficiency can be obtained. An SMIC 55 nm CMOS design kit and a VCMA-MTJ compact model described by Verilog-A language are used for hybrid simulation on the Cadence/Specter Platform. Simulation results in $0.7\times $ and $1.3\times $ of the improvements in data backup time and backup energy, respectively, compared with the efficient VCMA-MTJ-based MNV-FF. Two more improvements of $158.7\times $ and $19.6\times $ in data restore time and restore energy are also achieved in the same comparison.

中文翻译：

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具有电压控制磁各向异性的自适应写电路的高速，节能磁非易失性触发器

触发器（FF）占VLSI电路整体功耗的很大一部分。磁性隧道结（MTJ）可以与常规FF结合使用，以实现非易失性，几乎无限的写入时间和更高的能源效率。主流的MTJ切换机制包括自旋传递转矩（STT），自旋轨道转矩（SOT）和压控磁各向异性（VCMA）效应，其中前两种机制都面临着较大的写入能量和写入能量的缺点。潜伏。取而代之的是，利用VCMA效应来切换MTJ只需一个纳秒级的时间，并且能耗低，从而更加节能。在本文中，首先，提出了一种双级预充电感测放大器（DPCSA），与传统的相比，它减少了53.9％的感测延迟。其次，基于DPCSA，设计了具有自适应写电路的基于VCMA-MTJ的多位共享磁非易失性FF（MNV-FF），可实现备份和还原操作的高速和高能效。最后，通过扩展MNV-FF，可以获得具有高面积效率的磁性非易失性寄存器组（MNV-RG）。Verilog-A语言描述的SMIC 55 nm CMOS设计套件和VCMA-MTJ紧凑模型用于Cadence / Spectre平台上的混合仿真。模拟结果 Verilog-A语言描述的SMIC 55 nm CMOS设计套件和VCMA-MTJ紧凑模型用于Cadence / Spectre平台上的混合仿真。模拟结果 Verilog-A语言描述的SMIC 55 nm CMOS设计套件和VCMA-MTJ紧凑模型用于Cadence / Spectre平台上的混合仿真。模拟结果 $ 0.7 \次$ 和 $ 1.3 \次$ 与有效的基于VCMA-MTJ的MNV-FF相比，数据备份时间和备份能量分别得到了改善。的两个改进 $ 158.7 \次$ 和 $ 19.6 \次$ 在相同的比较中，还可以实现数据恢复时间和恢复能量方面的优势。