This paper demonstrates a wideband 2.4 GHz $2\times 9$ -bit Cartesian radio-frequency digital-to-analog converter (RFDAC). Active-under-coil integration is introduced in the physical implementation, where all key active circuitry is located underneath the matching-network transformer, achieving a core area of merely 0.35 mm ² . An $8\times $ analog linear interpolation at the RF rate is proposed to suppress replicas close to the carrier while avoiding any high-order and high-speed digital filters in digital processing back-end. The multi-port transformer is adopted in the matching network to improve the back-off efficiency. The measured peak output power and drain efficiency at the center frequency of 2.4 GHz are 17.47 dBm and 17.6% respectively, while the peak efficiency is 19.03%. Moreover, the 6-dB back-off efficiency is at 66% of that at the peak output power. The active-under-coil integration helps this RFDAC to achieve the smallest area among comparable prior arts.

中文翻译：

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在28nm CMOS中具有模拟线性内插的有源下线圈有源RFDAC

本文演示了一个宽带2.4 GHz 2美元/次9美元 位笛卡尔射频数模转换器（RFDAC）。在物理实现中引入了线圈下有源集成，其中所有关键有源电路都位于匹配网络变压器的下方，核心面积仅为0.35 mm ² 。一个 $ 8 \次$ 提出以RF速率进行模拟线性内插，以抑制靠近载波的副本，同时避免在数字处理后端使用任何高阶和高速数字滤波器。匹配网络中采用了多端口变压器，以提高退避效率。在中心频率为2.4 GHz时测得的峰值输出功率和漏极效率分别为17.47 dBm和17.6％，而峰值效率为19.03％。此外，6 dB的退避效率仅为峰值输出功率时的66％。线圈下的有源集成帮助该RFDAC达到了可比的现有技术中最小的面积。