Polar codes have been officially selected as the channel coding in 5G standard. To meet the requirements of enhanced mobile broadband (eMBB), most published polar decoder chips aim to improve throughput rate and error-correction performance. However, to meet with the requirements of another two 5G new radio (NR) application scenarios, ultra-reliable low-latency communications (URLLC), and massive machine-type communications (mMTC), the design features of low latency and energy efficiency are also desirable. In this article, we present a 7.8-13.6 pJ/b ultra-low latency and energy-efficient polar decoder fabricated in 40nm CMOS technology. By adopting the decoding algorithm of recurrent neural network-assisted belief propagation (RNN-BP), the learned scaling parameters can improve the convergence rate by 8 times with reasonable hardware and memory overhead. Then, by taking advantage of BP’s regular structure, we propose a fully-reconfigurable RNN-BP decoder architecture to support multiple code lengths with negligible hardware complexity. It contributes to 2- $8\times $ improved hardware utilization rate while providing a flexible adjustment between throughput and error-correction performance. At the architectural level, two optimization techniques for the design of the processing element (PE) are proposed to jointly reduce the chip’s area and power by 73% and 67%, respectively. From the measurement results, our reconfigurable RNN-BP polar decoder chip has $2.3\times $ , $2.3\times $ , and $10.0\times $ enhancement over prior designs in terms of latency, throughput rate, and energy efficiency. Consequently, our reconfigurable design has great potential to meet various 5G NR applications.

中文翻译：

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具有多码长支持的7.8–13.6 pJ / b超低延迟和可重构神经网络辅助极性解码器

极地码已被正式选择为5G标准中的信道编码。为了满足增强型移动宽带（eMBB）的要求，大多数已发布的极性解码器芯片旨在提高吞吐速率和纠错性能。但是，为了满足另外两个5G新无线电（NR）应用场景，超可靠的低延迟通信（URLLC）和大规模机器类型通信（mMTC）的要求，低延迟和高能效的设计特点是也可取。在本文中，我们介绍了采用40nm CMOS技术制造的7.8-13.6 pJ / b超低延迟和高能效极性解码器。通过采用递归神经网络辅助的信念传播（RNN-BP）的解码算法，学习的缩放参数可以在合理的硬件和内存开销下将收敛速度提高8倍。然后，通过利用BP的常规结构，我们提出了一种完全可重新配置的RNN-BP解码器体系结构，以支持可忽略的硬件复杂度的多个代码长度。它有助于2- $ 8 \次$ 在提高吞吐量和纠错性能之间灵活调整的同时，提高了硬件利用率。在体系结构级别，提出了两种用于处理元件（PE）设计的优化技术，以共同将芯片的面积和功耗分别减少73％和67％。从测量结果来看，我们的可重构RNN-BP极性解码器芯片具有 $ 2.3 \次$ ， $ 2.3 \次$ ， 和 $ 10.0 \次$ 在延迟，吞吐率和能源效率方面比以前的设计有所增强。因此，我们的可重构设计具有满足各种5G NR应用的巨大潜力。