In this paper, a 25 Gbps inductorless optical receiver analog front-end is presented. The inverter-based modified Cherry-Hooper amplifier is proposed and adopted as main stage of the optical receiver to extend the bandwidth by alleviating Miller capacitance. The optimization of shunt-feedback transimpedance amplifier is implemented by improving the gain bandwidth product of main amplifier. In multi-stage limiting amplifier, the staggered active feedback technique is used to boost the deteriorated bandwidth. Fabricated in a 55 nm CMOS technology, the whole chip occupies an area of 770 μm × 800 μm, and core area is only 100 μm × 400 μm. The measured 3-dB bandwidth reaches 21.7 GHz, sufficient for 25-Gbps operation. For an input voltage of 3 mV_p-p, the chip achieves a BER = 10⁻¹² at 25-Gbps PRBS7, and 320 mV differential output voltage is delivered. From the supply voltage of 1.2 V, the test chip consumes the power of 56 mW and exhibits the power efficiency of 2.3 pJ/s.

本文提出了一种25 Gbps无电感器光接收器模拟前端。提出并采用了基于反相器的改进型Cherry-Hooper放大器作为光接收器的主要级，以通过减轻米勒电容来扩展带宽。通过改善主放大器的增益带宽乘积来实现并联反馈互阻放大器的优化。在多级限幅放大器中，采用交错式有源反馈技术来提高恶化的带宽。制造在一个55纳米CMOS技术，全芯片770占用的面积 μ米×800  μ m和芯面积仅为100  μ米×400  μ米 测得的3 dB带宽达到21.7 GHz，足以进行25 Gbps的操作。对于3 mV _p-p的输入电压，芯片 在25 Gbps PRBS7时达到BER = 10 ^-12，并提供320 mV差分输出电压。从1.2 V的电源电压来看，测试芯片的功耗为56 mW，功率效率为2.3 pJ / s。