Recent advances in reprogrammable hardware (e.g., FPGAs) and memory technology (e.g., DDR4, HBM) promise to solve performance problems inherent to graph processing like irregular memory access patterns on traditional hardware (e.g., CPU). While several of these graph accelerators were proposed in recent years, it remains difficult to assess their performance and compare them on common graph workloads and accelerator platforms, due to few open source implementations and excessive implementation effort. In this work, we build on a simulation environment for graph processing accelerators, to make several existing accelerator approaches comparable. This allows us to study relevant performance dimensions such as partitioning schemes and memory technology, among others. The evaluation yields insights into the strengths and weaknesses of current graph processing accelerators along these dimensions, and features a novel in-depth comparison.

中文翻译：

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基于FPGA的图形处理加速器的内存访问模式的神秘化

可重编程硬件（例如FPGA）和存储器技术（例如DDR4，HBM）的最新进展有望解决图形处理固有的性能问题，例如传统硬件（例如CPU）上的不规则存储器访问模式。尽管近年来提出了几种这样的图形加速器，但是由于很少的开源实现和过多的实现工作，因此仍然难以评估它们的性能并在常见的图形工作负载和加速器平台上进行比较。在这项工作中，我们基于用于图形处理加速器的仿真环境，以使几种现有的加速器方法具有可比性。这使我们能够研究相关的性能维度，例如分区方案和内存技术。