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Performance Limit and Coding Schemes for Resistive Random-Access Memory Channels
IEEE Transactions on Communications ( IF 8.3 ) Pub Date : 2021-01-13 , DOI: 10.1109/tcomm.2021.3051413
Guanghui Song 1 , Kui Cai 1 , Xingwei Zhong 1 , Yu Jiang 1 , Jun Cheng 2
Affiliation  

Resistive random-access memory (ReRAM) is a promising candidate for the next generation non-volatile memory technology due to its simple read/write operations and high storage density. However, its crossbar array structure causes a severe interference effect known as the “sneak path.” In this paper, we propose channel coding techniques that can mitigate both the sneak-path interference and the channel noise. The main challenge is that the sneak-path interference is data-dependent, and also correlated within a memory array, and hence the conventional error correction coding scheme will be inadequate. In this work, we propose an across-array coding strategy that assigns a codeword to multiple independent memory arrays, and exploit a real-time channel estimation scheme to estimate the instantaneous status of the ReRAM channel. Since the coded bits from different arrays experience independent channels, a “diversity” gain can be obtained during decoding, and when the codeword is adequately distributed over different memory arrays, the code actually performs as that over an uncorrelated channel. By performing decoding based on the scheme of treating-interference-as-noise (TIN), the ReRAM channel over different memory arrays is equivalent to a block varying channel we defined, for which we propose both the capacity bounds and a coding scheme. The proposed coding scheme consists of a serial concatenation of an optimized error correction code with a data shaper, which enables the ReRAM system to achieve a near capacity limit storage efficiency.

中文翻译:

电阻性随机存取存储器通道的性能限制和编码方案

电阻式随机存取存储器(ReRAM)由于其简单的读/写操作和高存储密度,因此是下一代非易失性存储器技术的有希望的候选者。但是,其交叉阵列结构会产生严重的干扰效应,称为“潜行路径”。在本文中,我们提出了一种信道编码技术,该技术可以减轻潜行路径干扰和信道噪声。主要挑战是潜行路径干扰是数据相关的,并且在存储器阵列内也相关,因此常规的纠错编码方案将是不充分的。在这项工作中,我们提出了一种跨阵列编码策略,该策略将一个码字分配给多个独立的存储器阵列,并利用实时通道估计方案来估计ReRAM通道的瞬时状态。由于来自不同阵列的编码位会经历独立的通道,因此在解码过程中可以获得“分集”增益,并且当码字在不同的存储阵列上充分分布时,代码实际上会在不相关的通道上执行。通过基于噪声干扰处理(TIN)方案执行解码,不同存储阵列上的ReRAM通道等效于我们定义的块变化通道,为此我们建议了容量限制和编码方案。所提出的编码方案由优化的纠错码与数据整形器的串行连接组成,这使ReRAM系统能够达到接近容量极限的存储效率。当代码字适当地分布在不同的存储阵列上时,代码实际上会在不相关的通道上执行相同的操作。通过基于噪声干扰处理(TIN)方案执行解码,不同存储阵列上的ReRAM通道等效于我们定义的块变化通道,为此我们建议了容量限制和编码方案。所提出的编码方案由优化的纠错码与数据整形器的串行连接组成,这使ReRAM系统能够达到接近容量极限的存储效率。当代码字适当地分布在不同的存储阵列上时,代码实际上会在不相关的通道上执行相同的操作。通过基于噪声干扰处理(TIN)方案执行解码,不同存储阵列上的ReRAM通道等效于我们定义的块变化通道,为此我们建议了容量限制和编码方案。所提出的编码方案由优化的纠错码与数据整形器的串行连接组成,这使ReRAM系统能够达到接近容量极限的存储效率。在不同内存阵列上的ReRAM通道等效于我们定义的块变化通道,为此我们提出了容量限制和编码方案。所提出的编码方案由优化的纠错码与数据整形器的串行连接组成,这使ReRAM系统能够达到接近容量极限的存储效率。在不同内存阵列上的ReRAM通道等效于我们定义的块变化通道,为此我们提出了容量限制和编码方案。所提出的编码方案由优化的纠错码与数据整形器的串行连接组成,这使ReRAM系统能够达到接近容量极限的存储效率。
更新日期:2021-01-13
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