This article presents Lock-V, a heterogeneous fault tolerance architecture that explores a dual-core lockstep (DCLS) technique to mitigate single event upset (SEU) and common-mode failure (CMF) problems. The Lock-V was deployed in two versions, Lock-VA and Lock-VM by applying design diversity in two processor architectures at the instruction set architecture (ISA)-level. Lock-VA features an Arm Cortex-A9 with a RISC-V RV64GC, while Lock-VM includes an Arm Cortex-M3 along with a RISC-V RV32IMA processor. The solution explores field-programmable gate array (FPGA) technology to deploy softcore versions of the RISC-V processors, and dedicated accelerators for performing error detection and triggering the software rollback system used for error recovery. To test Lock-V in both versions, a fault-injection mechanism was implemented to cause bit-flips in the processor registers, a common problem usually present in heavy radiation environments.

本文介绍了Lock-V，这是一种异构的容错体系结构，它探索了双核锁步（DCLS）技术来减轻单事件失败（SEU）和共模故障（CMF）问题。通过在指令集体系结构（ISA）级别在两个处理器体系结构中应用设计多样性，可以将Lock-V部署为Lock-VA和Lock-VM两个版本。Lock-VA配备了带有RISC-V RV64GC的Arm Cortex-A9，而Lock-VM包含了一个RISC-V RV32IMA处理器的Arm Cortex-M3。该解决方案探索了现场可编程门阵列（FPGA）技术，以部署RISC-V处理器的软核版本，以及用于执行错误检测和触发用于错误恢复的软件回滚系统的专用加速器。要在两个版本中测试Lock-V，