Through Silicon Vias (TSVs) are crucial elements for the reliable operation and yield of three dimensional integrated circuits (3D ICs). Defects are a serious concern in TSV structures. A post-bond, parallel testing and diagnosis scheme is proposed in this work, for the detection and location of resistive open or short to substrate defects in TSVs, which is based on easily synthesizable all digital testing circuitry. The new testing method provides tolerance over process and temperature variations that may influence the embedded circuits. Extensive typical model simulations and Monte-Carlo analysis results, using the 65 nm technology of TSMC, prove the effectiveness of the new method. Additionally, two representative methods from the literature are simulated and compared to the proposed one, in terms of effectiveness, robustness, tolerance, cost and design for testability effort. The proposed scheme is proven to perform better based on all presented criteria.

硅通孔（TSV）是确保三维集成电路（3D IC）可靠运行和良率的关键要素。缺陷是TSV结构中的一个严重问题。在这项工作中，提出了一种后结合的并行测试和诊断方案，该方案用于检测和定位TSV中的电阻性开路或与基板短路的缺陷，该方案基于易于综合的所有数字测试电路。新的测试方法提供了对可能影响嵌入式电路的工艺和温度变化的容忍度。使用台积电65纳米技术的大量典型模型仿真和蒙特卡洛分析结果证明了该新方法的有效性。此外，从文献中模拟了两种代表性方法，并将其与提出的方法进行了比较，包括有效性，鲁棒性，耐受性，成本和可测试性的设计。基于所有提出的标准，所提出的方案被证明具有更好的性能。