A refresh free and scalable ultimate DRAM (uDRAM) with 1T1C bitcell is introduced in this paper. The memory uses the Negative Differential Resistance (NDR) property of Tunnel Field Effect Transistors (TFET) and storage capacitor leakage to retain data statically. The static data retention eliminates the need for refresh. The uDRAM allows more than 5x scaling of a storage capacitor in comparison to Dual-Data-Rate (DDR) and embedded DRAMs. This concept is further extended to design a 2T1C ultimate SRAM (uSRAM) and 3T1C ultimate CAM (uCAM). Area of 0.0275 μm ² , 0.07 μm ² and 0.104 μm ² are achieved for DRAM, SRAM and CAM bitcells, respectively, when implemented in TFET-compatible 28 nm FDSOI-CMOS process. The uDRAM achieves an estimated throughput gain up-to 9.94% in comparison with a CMOS DRAM, owing to refresh removal in the DDR configuration. The 2T1C SRAM with read and write cycle times of sub-2ns and sub-4ns are demonstrated. The results show ultra-low leakage of less than 1 fA/bit for the proposed designs.

中文翻译：

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基于隧道FET负微分电阻的1T1C无刷新DRAM，2T1C SRAM和3T1C CAM

本文介绍了具有1T1C位单元的无刷新且可扩展的终极DRAM（uDRAM）。存储器使用隧道场效应晶体管（TFET）的负差分电阻（NDR）属性和存储电容器泄漏来静态保留数据。静态数据保留消除了刷新的需要。与双数据速率（DDR）和嵌入式DRAM相比，uDRAM可使存储电容器的缩放比例超过5倍。该概念进一步扩展为设计2T1C极限SRAM（uSRAM）和3T1C极限CAM（uCAM）。的0.0275微米区域 ² ，0.07微米 ²和0.104微米 ²当采用与TFET兼容的28 nm FDSOI-CMOS工艺实现时，分别可实现DRAM，SRAM和CAM位单元的数据传输。由于DDR配置中的刷新去除，与CMOS DRAM相比，uDRAM估计可达到高达9.94％的吞吐量。演示了具有亚2ns和亚4ns的读写周期的2T1C SRAM。结果表明，对于拟议的设计，超低泄漏电流小于1 fA / bit。