This paper presents a two-stage enhanced gain bulk-driven floating gate OTA (EG-BDFG OTA) using flipped voltage follower (FVF). The gain of the OTA is increased with the help of a self-biased summing stage followed by a conventional common-source stage. To ensure the stability of the proposed two-stage OTA, cascode compensation technique is used. The circuit is designed and simulated in Cadence Virtuoso tool using UMC 0.18-μm CMOS technology library. The simulation results indicate that the proposed design has an improved voltage gain of 59dB that is 3.5 times more than that of the single-stage BDFG-FVF OTA. The linearity of the proposed OTA is almost maintained while enhancing the gain by 42dB. The circuit delivers −65dB of HD₃ and −56dB of THD when a 0.2-V_pp differential input signal of 1-MHz frequency is applied. The circuit is also verified for process variations at different corners with the aid of Monte Carlo and Corner analyses. The layout of the proposed EG-BDFG OTA is also drawn and presented in the paper.

中文翻译：

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一种低压两级增强增益大容量驱动浮栅OTA

本文介绍了一种使用翻转电压跟随器 (FVF) 的两级增强增益体驱动浮栅 OTA (EG-BDFG OTA)。OTA 的增益在自偏置求和级的帮助下增加，然后是传统的共源级。为了确保所提出的两级OTA的稳定性，使用了级联补偿技术。该电路使用 UMC 0.18-在 Cadence Virtuoso 工具中设计和仿真μm CMOS 技术库。仿真结果表明，所提出的设计的电压增益提高了 59dB是单级BDFG-FVF OTA的3.5倍。所提出的 OTA 的线性度几乎保持不变，同时将增益提高了 42D b。该电路提供-65_{HD 3}的 dB和-56应用 1MHz 频率的 0.2V _{pp差分输入信号时的 THD dB。}借助 Monte Carlo 和 Corner 分析，还验证了电路在不同角落的工艺变化。提出的 EG-BDFG OTA 的布局也在本文中绘制和呈现。