ABSTRACT

Managing the speed and power trade-off is becoming increasingly challenging as the power supply voltage (Vdd) is scaled down in each era. Existing logic circuits that address the trade-off require more power. A new logic circuit made up of one PMOS and two NMOS is evaluated while coupled to a typical power delivery network (PDN). Simulated in a 0.09 µm CMOS, the present circuit not only reduces the supply current but also achieves a constant delay than the CSL, MCML and CS-CMOS while the Vdd switches from 0.7 to 1.1 V. Besides, the power consumption and delay sustain a shift of 0.14µW and 0.3ps, respectively, following a 1^OC change in temperature. However, the power consumption reduces by 0.2µW for a Vdd drop of 1mV. But the effective supply voltage close to the circuit fluctuates as the PDN draws a sudden high current. This causes the delay to change and induces jitter in the output swing. The jitter introduced for a current ramp 0–40A in 10ns is 6.7ps. The usefulness of the present design is also observed by designing a latch, master-slave flip-flop (FF), frequency divider (FD) and ring oscillator (RO). Comparing the latch, FF, FD and RO built using the conventional, proposed designs and simulated in a 0.09-µm CMOS show the lowest power and delay.

摘要

随着电源电压 (Vdd) 在每个时代的缩减，管理速度和功率权衡变得越来越具有挑战性。解决折衷的现有逻辑电路需要更多功率。评估由一个 PMOS 和两个 NMOS 组成的新逻辑电路，同时耦合到典型的供电网络 (PDN)。在 0.09 µm CMOS 中模拟，本电路不仅降低了电源电流，而且在 Vdd 从 0.7 V 切换到 1.1 V 时，比 CSL、MCML 和 CS-CMOS 实现了恒定延迟。此外，功耗和延迟维持0.14µW 和 0.3ps 的偏移，分别在 1 ^O之后C 温度变化。然而，当 Vdd 下降 1mV 时，功耗降低了 0.2µW。但是，当 PDN 吸收突然的高电流时，靠近电路的有效电源电压会波动。这会导致延迟发生变化并在输出摆幅中引起抖动。10ns 内电流斜坡 0–40A 引入的抖动为 6.7ps。通过设计锁存器、主从触发器 (FF)、分频器 (FD) 和环形振荡器 (RO)，也可以观察到本设计的有用性。比较使用传统的建议设计构建并在 0.09-µm CMOS 中模拟的锁存器、FF、FD 和 RO，显示出最低的功耗和延迟。