ABSTRACT

The overall network effectiveness in any real time application is defined by the amount of precision used in computing and the capacity to sustain low cost hardware. Within this context optimisation method for floating point computing is starting to emerge gradually due to the enhanced precision level. Particularly with regard to FFT floating point arithmetic model calculation, hardware sophistication is forced to minimise the uncertainty penalty gap between fixed points – FFT floating point prototype. Hardware fusion systems are designed primarily for increasing the use rate of hardware throughout FPU arithmetic calculations. The proposed system to compute mantissa is actually achieved using which hardware counts are reduced in a complex multiplication process and afterwards the signed digit recoding can be reconfigured by a digital integer. Eventually, the technique of radix factorisation is integrated to minimise complex arithmetic associated with phases of FFT. The results show that the algorithm proposed shows decreased field, elevated frequency of operation and an increased level of accuracy. Ultimately, it is contrasted with efficient FPGA implementation that uses the capital and robustness of the proposed fused CSD FP models.

摘要

任何实时应用程序中的整体网络有效性由计算中使用的精度和维持低成本硬件的能力来定义。在这种情况下，由于精度水平的提高，浮点计算的优化方法开始逐渐出现。特别是在 FFT 浮点算法模型计算方面，硬件复杂性被迫最小化定点之间的不确定性惩罚差距——FFT 浮点原型。硬件融合系统主要设计用于提高整个 FPU 算术计算的硬件使用率。所提出的计算尾数的系统实际上是通过在复杂的乘法过程中减少硬件计数来实现的，然后可以通过数字整数重新配置有符号数字重新编码。最终，基数分解技术被集成以最小化与 FFT 相位相关的复杂算术。结果表明，所提出的算法显示出减小的磁场、提高的操作频率和提高的精度水平。最终，它与使用所提出的融合 CSD FP 模型的资本和稳健性的高效 FPGA 实现形成对比。